Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP54xx CM2 instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* CM2 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define OMAP54XX_CM_CORE_BASE		0x4a008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OMAP54XX_CM_CORE_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* CM_CORE instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OMAP54XX_CM_CORE_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OMAP54XX_CM_CORE_CKGEN_INST		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OMAP54XX_CM_CORE_COREAON_INST		0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OMAP54XX_CM_CORE_CORE_INST		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OMAP54XX_CM_CORE_IVA_INST		0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OMAP54XX_CM_CORE_CAM_INST		0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OMAP54XX_CM_CORE_DSS_INST		0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OMAP54XX_CM_CORE_GPU_INST		0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OMAP54XX_CM_CORE_L3INIT_INST		0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP54XX_CM_CORE_CUSTEFUSE_INST		0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OMAP54XX_CM_CORE_RESTORE_INST		0x1e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OMAP54XX_CM_CORE_INSTR_INST		0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* CM_CORE clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS		0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS		0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS		0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS		0x0a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* CM_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OMAP54XX_REVISION_CM_CORE_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET			0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* CM_CORE.CKGEN_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define OMAP54XX_CM_CLKSEL_USB_60MHZ				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OMAP54XX_CM_CLKMODE_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET			0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OMAP54XX_CM_IDLEST_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET			0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define OMAP54XX_CM_AUTOIDLE_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET			0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define OMAP54XX_CM_CLKSEL_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OMAP54XX_CM_DIV_M2_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET			0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OMAP54XX_CM_DIV_M3_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OMAP54XX_CM_DIV_H11_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET			0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OMAP54XX_CM_DIV_H12_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define OMAP54XX_CM_DIV_H13_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define OMAP54XX_CM_DIV_H14_DPLL_PER				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define OMAP54XX_CM_CLKMODE_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET			0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OMAP54XX_CM_IDLEST_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP54XX_CM_AUTOIDLE_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET			0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP54XX_CM_CLKSEL_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET			0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP54XX_CM_DIV_M2_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET			0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET			0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET			0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET			0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET			0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET		0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET		0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET		0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET			0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET		0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET			0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET			0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET		0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET		0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* CM_CORE.COREAON_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET	0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET	0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET	0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* CM_CORE.CORE_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET			0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET			0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET		0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET			0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP54XX_CM_IPU_STATICDEP_OFFSET			0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET			0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET			0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP54XX_CM_IPU_IPU_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET			0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP54XX_CM_DMA_STATICDEP_OFFSET			0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET			0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET		0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET			0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET			0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP54XX_CM_EMIF_DMM_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET		0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET			0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET			0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET		0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET			0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP54XX_CM_C2C_STATICDEP_OFFSET			0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET			0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET			0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP54XX_CM_C2C_C2C_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET		0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET		0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET			0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET			0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET		0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET		0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET		0x0638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET		0x0640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET			0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET		0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET		0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET		0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET		0x0748
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET	0x0750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET			0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET			0x0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET			0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET			0x0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET		0x0828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET			0x0830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET			0x0900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET			0x0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET		0x0928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET		0x0930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET			0x0938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET			0x0940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET			0x0948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET			0x0950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET			0x0958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP54XX_CM_L4PER_ELM_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET			0x0960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET			0x0968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET			0x0970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET			0x0978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET			0x0980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET			0x0988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET			0x09a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET			0x09a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET			0x09b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET			0x09b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET			0x09c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET			0x09f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET			0x09f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET			0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET			0x0a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET			0x0a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET			0x0a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET			0x0a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET			0x0a28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET			0x0a40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OMAP54XX_CM_L4PER_UART1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET			0x0a48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OMAP54XX_CM_L4PER_UART2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET			0x0a50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OMAP54XX_CM_L4PER_UART3_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET			0x0a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define OMAP54XX_CM_L4PER_UART4_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET			0x0a60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET			0x0a68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET			0x0a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define OMAP54XX_CM_L4PER_UART5_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET			0x0a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP54XX_CM_L4PER_UART6_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET			0x0a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET			0x0a84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET			0x0a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET			0x0aa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET			0x0aa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET		0x0ab0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET			0x0ab8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET			0x0ac0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET		0x0ac8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET		0x0ad8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* CM_CORE.IVA_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OMAP54XX_CM_IVA_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define OMAP54XX_CM_IVA_IVA_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define OMAP54XX_CM_IVA_SL2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* CM_CORE.CAM_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OMAP54XX_CM_CAM_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OMAP54XX_CM_CAM_ISS_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OMAP54XX_CM_CAM_FDIF_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OMAP54XX_CM_CAM_CAL_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* CM_CORE.DSS_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define OMAP54XX_CM_DSS_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define OMAP54XX_CM_DSS_DSS_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OMAP54XX_CM_DSS_BB2D_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* CM_CORE.GPU_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define OMAP54XX_CM_GPU_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define OMAP54XX_CM_GPU_GPU_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* CM_CORE.L3INIT_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET	0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET			0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL				OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET		0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL			OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL		OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif