Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP44xx CM2 instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2009-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2009-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *     or "OMAP4430".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* CM2 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define OMAP4430_CM2_BASE		0x4a008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OMAP44XX_CM2_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* CM2 instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OMAP4430_CM2_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OMAP4430_CM2_CKGEN_INST		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OMAP4430_CM2_ALWAYS_ON_INST	0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OMAP4430_CM2_CORE_INST		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define OMAP4430_CM2_IVAHD_INST		0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP4430_CM2_CAM_INST		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OMAP4430_CM2_DSS_INST		0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OMAP4430_CM2_GFX_INST		0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define OMAP4430_CM2_L3INIT_INST	0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OMAP4430_CM2_L4PER_INST		0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OMAP4430_CM2_CEFUSE_INST	0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define OMAP4430_CM2_RESTORE_INST	0x1e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OMAP4430_CM2_INSTR_INST		0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* CM2 clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP4430_CM2_CORE_L3_1_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OMAP4430_CM2_CORE_L3_2_CDOFFS		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OMAP4430_CM2_CORE_DUCATI_CDOFFS		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OMAP4430_CM2_CORE_SDMA_CDOFFS		0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OMAP4430_CM2_CORE_MEMIF_CDOFFS		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OMAP4430_CM2_CORE_D2D_CDOFFS		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OMAP4430_CM2_CORE_L4CFG_CDOFFS		0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS	0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OMAP4430_CM2_CAM_CAM_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OMAP4430_CM2_DSS_DSS_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OMAP4430_CM2_GFX_GFX_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OMAP4430_CM2_L4PER_L4PER_CDOFFS		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS		0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* CM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* CM2.OCP_SOCKET_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OMAP4_REVISION_CM2_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OMAP4430_REVISION_CM2				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OMAP4430_CM_CM2_PROFILING_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* CM2.CKGEN_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OMAP4430_CM_CLKSEL_USB_60MHZ			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define OMAP4_CM_SCALE_FCLK_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OMAP4430_CM_SCALE_FCLK				OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define OMAP4430_CM_CORE_DVFS_PERF1			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET			0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OMAP4430_CM_CORE_DVFS_PERF2			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET			0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OMAP4430_CM_CORE_DVFS_PERF3			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET			0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define OMAP4430_CM_CORE_DVFS_PERF4			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OMAP4430_CM_CORE_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define OMAP4430_CM_IVA_DVFS_PERF_TESLA			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define OMAP4430_CM_IVA_DVFS_PERF_ABE			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OMAP4430_CM_IVA_DVFS_CURRENT			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define OMAP4430_CM_CLKMODE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET			0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP4430_CM_IDLEST_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP4430_CM_AUTOIDLE_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET			0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP4430_CM_CLKSEL_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP4430_CM_DIV_M2_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET			0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP4430_CM_DIV_M3_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP4430_CM_DIV_M4_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET			0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP4430_CM_DIV_M5_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP4430_CM_DIV_M6_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP4430_CM_DIV_M7_DPLL_PER			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP4430_CM_CLKMODE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET			0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP4430_CM_IDLEST_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP4430_CM_AUTOIDLE_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET			0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP4430_CM_CLKSEL_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET			0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP4430_CM_DIV_M2_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP4430_CM_CLKDCOLDO_DPLL_USB			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET		0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP4430_CM_IDLEST_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET	0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET	0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* CM2.ALWAYS_ON_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP4430_CM_ALWON_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* CM2.CORE_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OMAP4430_CM_L3_1_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP4430_CM_L3_1_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP4430_CM_L3_1_L3_1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET			0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define OMAP4430_CM_L3_2_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET			0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP4430_CM_L3_2_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP4430_CM_L3_2_L3_2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP4430_CM_L3_2_GPMC_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET		0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP4430_CM_DUCATI_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP4_CM_DUCATI_STATICDEP_OFFSET		0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP4430_CM_DUCATI_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET		0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP4430_CM_DUCATI_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET		0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET			0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP4430_CM_SDMA_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP4_CM_SDMA_STATICDEP_OFFSET			0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP4430_CM_SDMA_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET			0x0308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP4430_CM_SDMA_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET		0x0320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP4430_CM_SDMA_SDMA_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET			0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP4430_CM_MEMIF_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET		0x0420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP4430_CM_MEMIF_DMM_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET		0x0428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET		0x0430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET		0x0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET		0x0440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP4430_CM_MEMIF_DLL_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET		0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET		0x0458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET		0x0460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET			0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define OMAP4430_CM_D2D_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define OMAP4_CM_D2D_STATICDEP_OFFSET			0x0504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define OMAP4430_CM_D2D_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET			0x0508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OMAP4430_CM_D2D_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET		0x0520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OMAP4430_CM_D2D_SAD2D_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET		0x0528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET		0x0530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET			0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define OMAP4430_CM_L4CFG_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET		0x0608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define OMAP4430_CM_L4CFG_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET		0x0620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET		0x0628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET		0x0630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET		0x0638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define OMAP4430_CM_L3INSTR_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET		0x0720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET	0x0728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET		0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* CM2.IVAHD_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define OMAP4430_CM_IVAHD_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define OMAP4_CM_IVAHD_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define OMAP4430_CM_IVAHD_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define OMAP4430_CM_IVAHD_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define OMAP4430_CM_IVAHD_SL2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* CM2.CAM_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define OMAP4430_CM_CAM_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define OMAP4_CM_CAM_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define OMAP4430_CM_CAM_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OMAP4430_CM_CAM_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define OMAP4430_CM_CAM_ISS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP4430_CM_CAM_FDIF_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* CM2.DSS_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define OMAP4430_CM_DSS_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define OMAP4_CM_DSS_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define OMAP4430_CM_DSS_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define OMAP4430_CM_DSS_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define OMAP4430_CM_DSS_DSS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define OMAP4430_CM_DSS_DEISS_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* CM2.GFX_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define OMAP4430_CM_GFX_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define OMAP4_CM_GFX_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define OMAP4430_CM_GFX_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define OMAP4430_CM_GFX_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OMAP4430_CM_GFX_GFX_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* CM2.L3INIT_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OMAP4430_CM_L3INIT_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define OMAP4_CM_L3INIT_STATICDEP_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define OMAP4430_CM_L3INIT_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define OMAP4430_CM_L3INIT_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define OMAP4430_CM_L3INIT_HSI_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define OMAP4430_CM_L3INIT_P1500_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define OMAP4430_CM_L3INIT_SATA_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET	0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET	0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL	OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* CM2.L4PER_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define OMAP4430_CM_L4PER_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define OMAP4430_CM_L4PER_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define OMAP4430_CM_L4PER_ADC_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define OMAP4430_CM_L4PER_ELM_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OMAP4430_CM_L4PER_HECC1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OMAP4430_CM_L4PER_HECC2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define OMAP4430_CM_L4PER_I2C1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OMAP4430_CM_L4PER_I2C2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OMAP4430_CM_L4PER_I2C3_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define OMAP4430_CM_L4PER_I2C4_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define OMAP4430_CM_L4PER_L4PER_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET		0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET		0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET		0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define OMAP4430_CM_L4PER_MGATE_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET		0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET		0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET		0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET		0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET		0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define OMAP4430_CM_L4PER_UART1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET		0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define OMAP4430_CM_L4PER_UART2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET		0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define OMAP4430_CM_L4PER_UART3_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET		0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define OMAP4430_CM_L4PER_UART4_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET		0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET		0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define OMAP4430_CM_L4PER_I2C5_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET			0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define OMAP4430_CM_L4SEC_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define OMAP4_CM_L4SEC_STATICDEP_OFFSET			0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define OMAP4430_CM_L4SEC_STATICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET		0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define OMAP4430_CM_L4SEC_DYNAMICDEP			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET		0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define OMAP4430_CM_L4SEC_AES1_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET		0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define OMAP4430_CM_L4SEC_AES2_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET		0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET		0x01b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET		0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define OMAP4430_CM_L4SEC_RNG_CLKCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET		0x01c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET		0x01d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* CM2.CEFUSE_CM2 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define OMAP4430_CM_CEFUSE_CLKSTCTRL			OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL		OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #endif