Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * DRA7xx CM1 instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* CM1 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRA7XX_CM_CORE_AON_BASE		0x4a005000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DRA7XX_CM_CORE_AON_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* CM_CORE_AON instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DRA7XX_CM_CORE_AON_CKGEN_INST		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DRA7XX_CM_CORE_AON_MPU_INST		0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DRA7XX_CM_CORE_AON_DSP1_INST		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DRA7XX_CM_CORE_AON_IPU_INST		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DRA7XX_CM_CORE_AON_DSP2_INST		0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRA7XX_CM_CORE_AON_EVE1_INST		0x0640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DRA7XX_CM_CORE_AON_EVE2_INST		0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DRA7XX_CM_CORE_AON_EVE3_INST		0x06c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DRA7XX_CM_CORE_AON_EVE4_INST		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DRA7XX_CM_CORE_AON_RTC_INST		0x0740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DRA7XX_CM_CORE_AON_VPE_INST		0x0760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DRA7XX_CM_CORE_AON_RESTORE_INST		0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DRA7XX_CM_CORE_AON_INSTR_INST		0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* CM_CORE_AON clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* CM_CORE_AON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DRA7XX_REVISION_CM_CORE_AON_OFFSET		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL		DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET		0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET		0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET		0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET		0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DRA7XX_CM_CLKSEL_CORE_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DRA7XX_CM_CLKSEL_CORE				DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DRA7XX_CM_CLKSEL_ABE_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DRA7XX_CM_CLKSEL_ABE				DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DRA7XX_CM_DLL_CTRL_OFFSET			0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DRA7XX_CM_CLKMODE_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET		0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define DRA7XX_CM_IDLEST_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DRA7XX_CM_AUTOIDLE_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DRA7XX_CM_CLKSEL_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET		0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DRA7XX_CM_DIV_M2_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET		0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DRA7XX_CM_DIV_M3_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET		0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DRA7XX_CM_DIV_H11_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DRA7XX_CM_DIV_H12_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define DRA7XX_CM_DIV_H13_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET		0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DRA7XX_CM_DIV_H14_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define DRA7XX_CM_DIV_H21_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET		0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DRA7XX_CM_DIV_H22_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DRA7XX_CM_DIV_H23_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET		0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DRA7XX_CM_DIV_H24_DPLL_CORE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DRA7XX_CM_CLKMODE_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DRA7XX_CM_IDLEST_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DRA7XX_CM_AUTOIDLE_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DRA7XX_CM_CLKSEL_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DRA7XX_CM_DIV_M2_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DRA7XX_CM_BYPCLK_DPLL_MPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DRA7XX_CM_CLKMODE_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET		0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DRA7XX_CM_IDLEST_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DRA7XX_CM_AUTOIDLE_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET		0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DRA7XX_CM_CLKSEL_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET		0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DRA7XX_CM_DIV_M2_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DRA7XX_CM_DIV_M3_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET	0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET	0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET		0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DRA7XX_CM_BYPCLK_DPLL_IVA			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DRA7XX_CM_CLKMODE_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET		0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DRA7XX_CM_IDLEST_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET		0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DRA7XX_CM_AUTOIDLE_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET		0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DRA7XX_CM_CLKSEL_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET		0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DRA7XX_CM_DIV_M2_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET		0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DRA7XX_CM_DIV_M3_DPLL_ABE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET	0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET	0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DRA7XX_CM_CLKMODE_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRA7XX_CM_IDLEST_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRA7XX_CM_AUTOIDLE_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DRA7XX_CM_CLKSEL_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DRA7XX_CM_DIV_M2_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET		0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DRA7XX_CM_DIV_M3_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET		0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DRA7XX_CM_DIV_H11_DPLL_DDR			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET		0x0134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DRA7XX_CM_CLKMODE_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET		0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DRA7XX_CM_IDLEST_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET		0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRA7XX_CM_AUTOIDLE_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET		0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DRA7XX_CM_CLKSEL_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET		0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DRA7XX_CM_DIV_M2_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET		0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define DRA7XX_CM_DIV_M3_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET	0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET	0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET		0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define DRA7XX_CM_BYPCLK_DPLL_DSP			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET		0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define DRA7XX_CM_RESTORE_ST_OFFSET			0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET		0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define DRA7XX_CM_CLKMODE_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET		0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define DRA7XX_CM_IDLEST_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET		0x018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define DRA7XX_CM_AUTOIDLE_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET		0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define DRA7XX_CM_CLKSEL_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET		0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define DRA7XX_CM_DIV_M2_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET		0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DRA7XX_CM_DIV_M3_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET	0x019c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET	0x01a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET		0x01a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DRA7XX_CM_BYPCLK_DPLL_EVE			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET		0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DRA7XX_CM_CLKMODE_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET		0x01ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define DRA7XX_CM_IDLEST_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET		0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DRA7XX_CM_AUTOIDLE_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET		0x01b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DRA7XX_CM_CLKSEL_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET		0x01b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DRA7XX_CM_DIV_M2_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET		0x01bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DRA7XX_CM_DIV_M3_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET		0x01c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define DRA7XX_CM_DIV_H11_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET		0x01c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define DRA7XX_CM_DIV_H12_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET		0x01c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DRA7XX_CM_DIV_H13_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET		0x01cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DRA7XX_CM_DIV_H14_DPLL_GMAC			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET	0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET	0x01d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET		0x01d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DRA7XX_CM_CLKMODE_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET		0x01dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DRA7XX_CM_IDLEST_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET		0x01e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DRA7XX_CM_AUTOIDLE_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET		0x01e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DRA7XX_CM_CLKSEL_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET		0x01e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DRA7XX_CM_DIV_M2_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET		0x01ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DRA7XX_CM_DIV_M3_DPLL_GPU			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET	0x01f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET	0x01f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DRA7XX_CM_MPU_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRA7XX_CM_MPU_MPU_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET	0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL		DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define DRA7XX_CM_DSP1_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DRA7XX_CM_DSP1_DSP1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRA7XX_CM_IPU1_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DRA7XX_CM_IPU1_IPU1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET		0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define DRA7XX_CM_IPU_MCASP1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET		0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DRA7XX_CM_IPU_TIMER5_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DRA7XX_CM_IPU_TIMER6_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET		0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DRA7XX_CM_IPU_TIMER7_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET		0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DRA7XX_CM_IPU_TIMER8_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET		0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DRA7XX_CM_IPU_I2C5_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DRA7XX_CM_IPU_UART6_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DRA7XX_CM_DSP2_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DRA7XX_CM_DSP2_DSP2_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DRA7XX_CM_EVE1_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DRA7XX_CM_EVE1_EVE1_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DRA7XX_CM_EVE2_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define DRA7XX_CM_EVE2_EVE2_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define DRA7XX_CM_EVE3_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DRA7XX_CM_EVE3_EVE3_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define DRA7XX_CM_EVE4_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define DRA7XX_CM_EVE4_EVE4_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DRA7XX_CM_RTC_RTCSS_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define DRA7XX_CM_VPE_VPE_CLKCTRL			DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define DRA7XX_CM_VPE_STATICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif