Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * OMAP54xx CM1 instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* CM1 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define OMAP54XX_CM_CORE_AON_BASE		0x4a004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* CM_CORE_AON instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define OMAP54XX_CM_CORE_AON_CKGEN_INST		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define OMAP54XX_CM_CORE_AON_MPU_INST		0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define OMAP54XX_CM_CORE_AON_DSP_INST		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define OMAP54XX_CM_CORE_AON_ABE_INST		0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OMAP54XX_CM_CORE_AON_RESTORE_INST	0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OMAP54XX_CM_CORE_AON_INSTR_INST		0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* CM_CORE_AON clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* CM_CORE_AON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OMAP54XX_REVISION_CM_CORE_AON_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET	0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL		OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET			0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET		0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET		0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET		0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET		0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET	0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET		0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET		0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET	0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET	0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET		0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET		0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET		0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET		0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET		0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET	0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET	0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET	0x00d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET	0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET	0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET	0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET	0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET	0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET	0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET	0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define OMAP54XX_CM_CLKSEL_CORE_OFFSET				0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define OMAP54XX_CM_CLKSEL_CORE					OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define OMAP54XX_CM_CLKSEL_ABE_OFFSET				0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define OMAP54XX_CM_CLKSEL_ABE					OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define OMAP54XX_CM_DLL_CTRL_OFFSET				0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OMAP54XX_CM_CLKMODE_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET			0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OMAP54XX_CM_IDLEST_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OMAP54XX_CM_AUTOIDLE_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET			0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OMAP54XX_CM_CLKSEL_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define OMAP54XX_CM_DIV_M2_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET			0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define OMAP54XX_CM_DIV_M3_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OMAP54XX_CM_DIV_H11_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET			0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define OMAP54XX_CM_DIV_H12_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OMAP54XX_CM_DIV_H13_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET			0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP54XX_CM_DIV_H14_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET		0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET		0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP54XX_CM_DIV_H21_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET			0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP54XX_CM_DIV_H22_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP54XX_CM_DIV_H23_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET			0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP54XX_CM_DIV_H24_DPLL_CORE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP54XX_CM_CLKMODE_DPLL_MPU				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET			0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP54XX_CM_IDLEST_DPLL_MPU				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET			0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP54XX_CM_AUTOIDLE_DPLL_MPU				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET			0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP54XX_CM_CLKSEL_DPLL_MPU				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP54XX_CM_DIV_M2_DPLL_MPU				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET		0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP54XX_CM_BYPCLK_DPLL_MPU				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET			0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP54XX_CM_CLKMODE_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET			0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP54XX_CM_IDLEST_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET			0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP54XX_CM_AUTOIDLE_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET			0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP54XX_CM_CLKSEL_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET			0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP54XX_CM_DIV_H11_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET			0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP54XX_CM_DIV_H12_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP54XX_CM_BYPCLK_DPLL_IVA				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET			0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP54XX_CM_CLKMODE_DPLL_ABE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET			0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP54XX_CM_IDLEST_DPLL_ABE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET			0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP54XX_CM_AUTOIDLE_DPLL_ABE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET			0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP54XX_CM_CLKSEL_DPLL_ABE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET			0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP54XX_CM_DIV_M2_DPLL_ABE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET			0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP54XX_CM_DIV_M3_DPLL_ABE				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET		0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET		0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET			0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET			0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET			0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP54XX_CM_RESTORE_ST_OFFSET				0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP54XX_CM_MPU_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define OMAP54XX_CM_MPU_MPU_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET		0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL			OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP54XX_CM_DSP_STATICDEP_OFFSET			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET			0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define OMAP54XX_CM_DSP_DSP_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET			0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET			0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP54XX_CM_ABE_AESS_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET			0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP54XX_CM_ABE_MCPDM_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET			0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define OMAP54XX_CM_ABE_DMIC_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET			0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP54XX_CM_ABE_MCASP_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET			0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET			0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET			0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET			0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL			OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET			0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP54XX_CM_ABE_TIMER5_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET			0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP54XX_CM_ABE_TIMER6_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET			0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP54XX_CM_ABE_TIMER7_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET			0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP54XX_CM_ABE_TIMER8_CLKCTRL				OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET		0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL			OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif