^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP44xx CM1 instance offset macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * or "OMAP4430".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* CM1 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP4430_CM1_BASE 0x4a004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP44XX_CM1_REGADDR(inst, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* CM1 instances */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP4430_CM1_CKGEN_INST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP4430_CM1_MPU_INST 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP4430_CM1_TESLA_INST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP4430_CM1_ABE_INST 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP4430_CM1_RESTORE_INST 0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP4430_CM1_INSTR_INST 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* CM1 clockdomain register offsets (from instance start) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* CM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* CM1.OCP_SOCKET_CM1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP4_REVISION_CM1_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* CM1.CKGEN_CM1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* CM1.MPU_CM1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* CM1.TESLA_CM1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* CM1.ABE_CM1 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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