Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP2+ Clock Management prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2007-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Written by Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ARCH_ASM_MACH_OMAP2_CM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ARCH_ASM_MACH_OMAP2_CM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * PRCM to request that a module exit the inactive state in the case of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * OMAP2 & 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * In the case of OMAP4 this is the max duration in microseconds for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * module to reach the functionnal state from an inactive state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX_MODULE_READY_TIME		2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "prcm-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) extern struct omap_domain_base cm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) extern struct omap_domain_base cm2_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * the PRCM to request that a module enter the inactive state in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * case of OMAP2 & 3.  In the case of OMAP4 this is the max duration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * in microseconds for the module to reach the inactive state from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * a functional state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * kernel init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MAX_MODULE_DISABLE_TIME		5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)  * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)  * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)  * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * @module_enable: ptr to the SoC CM-specific module_enable impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  * @module_disable: ptr to the SoC CM-specific module_disable impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct cm_ll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				u8 *idlest_reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 				 u8 idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 				u8 idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			       u8 *idlest_reg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			      u8 idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			     u8 idlest_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern int cm_register(const struct cm_ll_data *cld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) extern int cm_unregister(const struct cm_ll_data *cld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int omap_cm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int omap2_cm_base_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif