Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * DRA7xx Clock Management register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRA7XX_ATL_STATDEP_SHIFT				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRA7XX_CAM_STATDEP_SHIFT				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRA7XX_DSP1_STATDEP_SHIFT				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRA7XX_DSP2_STATDEP_SHIFT				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRA7XX_DSS_STATDEP_SHIFT				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRA7XX_EMIF_STATDEP_SHIFT				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRA7XX_EVE1_STATDEP_SHIFT				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRA7XX_EVE2_STATDEP_SHIFT				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRA7XX_EVE3_STATDEP_SHIFT				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRA7XX_EVE4_STATDEP_SHIFT				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRA7XX_GMAC_STATDEP_SHIFT				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRA7XX_GPU_STATDEP_SHIFT				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRA7XX_IPU1_STATDEP_SHIFT				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRA7XX_IPU2_STATDEP_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRA7XX_IPU_STATDEP_SHIFT				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRA7XX_IVA_STATDEP_SHIFT				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRA7XX_L3INIT_STATDEP_SHIFT				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DRA7XX_L3MAIN1_STATDEP_SHIFT				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRA7XX_L4CFG_STATDEP_SHIFT				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DRA7XX_L4PER2_STATDEP_SHIFT				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRA7XX_L4PER3_STATDEP_SHIFT				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRA7XX_L4PER_STATDEP_SHIFT				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DRA7XX_L4SEC_STATDEP_SHIFT				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRA7XX_PCIE_STATDEP_SHIFT				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DRA7XX_VPE_STATDEP_SHIFT				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRA7XX_WKUPAON_STATDEP_SHIFT				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif