^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP54xx Clock Management register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Rajendra Nayak (rnayak@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP54XX_ABE_STATDEP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP54XX_CLKSEL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP54XX_CLKSEL_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP54XX_CLKSEL_0_0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP54XX_CLKSEL_DIV_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP54XX_CLKSEL_FCLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP54XX_CLKSEL_OPP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP54XX_DIVHS_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OMAP54XX_DSP_STATDEP_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP54XX_DSS_STATDEP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP54XX_EMIF_STATDEP_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP54XX_GPU_STATDEP_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP54XX_IPU_STATDEP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OMAP54XX_IVA_STATDEP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP54XX_L3INIT_STATDEP_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP54XX_L4CFG_STATDEP_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OMAP54XX_L4PER_STATDEP_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OMAP54XX_L4SEC_STATDEP_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP54XX_SYS_CLKSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags