Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * AM33XX Power Management register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is automatically generated from the AM33XX hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AM33XX_CLKOUT2DIV_SHIFT				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AM33XX_CLKOUT2DIV_WIDTH				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AM33XX_CLKOUT2EN_SHIFT				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AM33XX_CLKOUT2SOURCE_MASK			(0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AM33XX_CLKSEL_0_0_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AM33XX_CLKSEL_0_0_WIDTH				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AM33XX_CLKSEL_0_0_MASK				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AM33XX_CLKSEL_0_1_MASK				(3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AM33XX_CLKSEL_0_2_MASK				(7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AM33XX_CLKSEL_GFX_FCLK_MASK			(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AM33XX_CLKTRCTRL_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AM33XX_CLKTRCTRL_MASK				(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AM33XX_DPLL_CLKOUT_DIV_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AM33XX_DPLL_CLKOUT_DIV_WIDTH			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AM33XX_DPLL_DIV_MASK				(0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AM33XX_DPLL_PER_DIV_MASK			(0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AM33XX_DPLL_EN_MASK				(0x7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AM33XX_DPLL_MULT_MASK				(0x7ff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AM33XX_DPLL_MULT_PERIPH_MASK			(0xfff << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AM33XX_IDLEST_SHIFT				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AM33XX_IDLEST_MASK				(0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AM33XX_MODULEMODE_SHIFT				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AM33XX_MODULEMODE_MASK				(0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AM33XX_STM_PMD_CLKSEL_SHIFT			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AM33XX_STM_PMD_CLKSEL_WIDTH			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AM33XX_ST_DPLL_CLK_MASK				(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AM33XX_TRC_PMD_CLKSEL_SHIFT			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AM33XX_TRC_PMD_CLKSEL_WIDTH			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif