^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * OMAP24XX Clock Management register bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2007 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Written by Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OMAP24XX_EN_DSS1_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OMAP24XX_ST_MAILBOXES_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OMAP24XX_ST_HDQ_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OMAP2420_ST_I2C2_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OMAP2430_ST_I2CHS1_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OMAP2420_ST_I2C1_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP2430_ST_I2CHS2_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP24XX_ST_MCBSP2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP24XX_ST_MCBSP1_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP2430_ST_MCBSP5_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OMAP2430_ST_MCBSP4_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OMAP2430_ST_MCBSP3_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OMAP24XX_ST_AES_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OMAP24XX_ST_RNG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP24XX_ST_SHA_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OMAP24XX_ST_MPU_WDT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OMAP24XX_ST_32KSYNC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP24XX_EN_54M_PLL_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP24XX_EN_96M_PLL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP24XX_ST_54M_APLL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP24XX_ST_96M_APLL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP24XX_AUTO_DPLL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif