Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * TI81XX Clock Domain data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_81XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "cm81xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Note that 814x seems to have HWSUP_SWSUP for many clockdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * while 816x does not. According to the TRM, 816x only has HWSUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * for ALWON_L3_FAST. Also note that the TI tree clockdomains81xx.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * seems to have the related ifdef the wrong way around claiming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * 816x supports HWSUP while 814x does not. For now, we only set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * HWSUP for ALWON_L3_FAST as that seems to be supported for both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * dm814x and dm816x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Common for 81xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct clockdomain alwon_l3_slow_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.name		= "alwon_l3s_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.clkdm_offs	= TI81XX_CM_ALWON_L3_SLOW_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct clockdomain alwon_l3_med_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.name		= "alwon_l3_med_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.clkdm_offs	= TI81XX_CM_ALWON_L3_MED_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static struct clockdomain alwon_l3_fast_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.name		= "alwon_l3_fast_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.clkdm_offs	= TI81XX_CM_ALWON_L3_FAST_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.flags		= CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static struct clockdomain alwon_ethernet_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.name		= "alwon_ethernet_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.clkdm_offs	= TI81XX_CM_ETHERNET_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static struct clockdomain mmu_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.name		= "mmu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.clkdm_offs	= TI81XX_CM_MMU_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static struct clockdomain mmu_cfg_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.name		= "mmu_cfg_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.clkdm_offs	= TI81XX_CM_MMUCFG_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static struct clockdomain default_l3_slow_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.name		= "default_l3_slow_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.pwrdm		= { .name = "default_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.clkdm_offs	= TI816X_CM_DEFAULT_L3_SLOW_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static struct clockdomain default_sata_81xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.name		= "default_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.pwrdm		= { .name = "default_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.clkdm_offs	= TI816X_CM_DEFAULT_SATA_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 816x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct clockdomain alwon_mpu_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.name		= "alwon_mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.pwrdm		= { .name = "alwon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.cm_inst	= TI81XX_CM_ALWON_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.clkdm_offs	= TI81XX_CM_ALWON_MPU_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct clockdomain active_gem_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.name		= "active_gem_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.pwrdm		= { .name = "active_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.cm_inst	= TI81XX_CM_ACTIVE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.clkdm_offs	= TI816X_CM_ACTIVE_GEM_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static struct clockdomain ivahd0_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.name		= "ivahd0_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.pwrdm		= { .name = "ivahd0_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.cm_inst	= TI816X_CM_IVAHD0_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.clkdm_offs	= TI816X_CM_IVAHD0_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct clockdomain ivahd1_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.name		= "ivahd1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.pwrdm		= { .name = "ivahd1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.cm_inst	= TI816X_CM_IVAHD1_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.clkdm_offs	= TI816X_CM_IVAHD1_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct clockdomain ivahd2_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.name		= "ivahd2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.pwrdm		= { .name = "ivahd2_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.cm_inst	= TI816X_CM_IVAHD2_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.clkdm_offs	= TI816X_CM_IVAHD2_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct clockdomain sgx_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.name		= "sgx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.pwrdm		= { .name = "sgx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.cm_inst	= TI81XX_CM_SGX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.clkdm_offs	= TI816X_CM_SGX_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct clockdomain default_l3_med_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name		= "default_l3_med_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.pwrdm		= { .name = "default_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.clkdm_offs	= TI816X_CM_DEFAULT_L3_MED_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct clockdomain default_ducati_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.name		= "default_ducati_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.pwrdm		= { .name = "default_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.clkdm_offs	= TI816X_CM_DEFAULT_DUCATI_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clockdomain default_pci_816x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.name		= "default_pci_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.pwrdm		= { .name = "default_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.cm_inst	= TI81XX_CM_DEFAULT_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.clkdm_offs	= TI816X_CM_DEFAULT_PCI_CLKDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.flags		= CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clockdomain *clockdomains_ti814x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	&alwon_l3_slow_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	&alwon_l3_med_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	&alwon_l3_fast_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	&alwon_ethernet_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	&mmu_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	&mmu_cfg_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	&default_l3_slow_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	&default_sata_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void __init ti814x_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	clkdm_register_clkdms(clockdomains_ti814x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clockdomain *clockdomains_ti816x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	&alwon_mpu_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	&alwon_l3_slow_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	&alwon_l3_med_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	&alwon_l3_fast_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	&alwon_ethernet_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	&mmu_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	&mmu_cfg_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	&active_gem_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	&ivahd0_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	&ivahd1_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	&ivahd2_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	&sgx_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	&default_l3_med_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	&default_ducati_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	&default_pci_816x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	&default_l3_slow_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	&default_sata_81xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __init ti816x_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	clkdm_register_platform_funcs(&am33xx_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	clkdm_register_clkdms(clockdomains_ti816x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif