^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DRA7xx Clock domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Generated by code originally written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Abhijit Pagare (abhijitpagare@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "cm1_7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "cm2_7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "cm-regbits-7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "prm7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "prcm_mpu7xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Static Dependencies for DRA7xx Clock Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct clkdm_dep cam_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct clkdm_dep dma_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .clkdm_name = "ipu2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .clkdm_name = "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .clkdm_name = "atl_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .clkdm_name = "cam_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .clkdm_name = "dsp2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .clkdm_name = "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .clkdm_name = "ipu2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .clkdm_name = "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .clkdm_name = "vpe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { .clkdm_name = "atl_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .clkdm_name = "cam_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .clkdm_name = "dsp1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .clkdm_name = "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .clkdm_name = "ipu2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .clkdm_name = "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .clkdm_name = "vpe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct clkdm_dep dss_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clkdm_dep eve1_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct clkdm_dep eve2_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct clkdm_dep eve3_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct clkdm_dep eve4_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clkdm_dep gmac_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct clkdm_dep gpu_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .clkdm_name = "atl_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .clkdm_name = "dsp1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .clkdm_name = "dsp2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .clkdm_name = "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .clkdm_name = "ipu2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .clkdm_name = "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .clkdm_name = "vpe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .clkdm_name = "atl_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .clkdm_name = "dsp1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .clkdm_name = "dsp2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .clkdm_name = "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { .clkdm_name = "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { .clkdm_name = "vpe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct clkdm_dep iva_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct clkdm_dep l3init_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .clkdm_name = "dsp1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { .clkdm_name = "dsp2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { .clkdm_name = "ipu2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct clkdm_dep mpu_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .clkdm_name = "cam_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .clkdm_name = "dsp1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .clkdm_name = "dsp2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .clkdm_name = "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .clkdm_name = "ipu2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { .clkdm_name = "pcie_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { .clkdm_name = "vpe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct clkdm_dep pcie_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { .clkdm_name = "atl_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { .clkdm_name = "cam_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { .clkdm_name = "dsp1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { .clkdm_name = "dsp2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { .clkdm_name = "eve1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .clkdm_name = "eve2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .clkdm_name = "eve3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { .clkdm_name = "eve4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .clkdm_name = "gmac_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .clkdm_name = "ipu1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { .clkdm_name = "l4per2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { .clkdm_name = "vpe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct clkdm_dep vpe_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { .clkdm_name = "l4per3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct clockdomain l4per3_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "l4per3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pwrdm = { .name = "l4per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct clockdomain l4per2_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = "l4per2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .pwrdm = { .name = "l4per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .wkdep_srcs = l4per2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .sleepdep_srcs = l4per2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct clockdomain mpu0_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "mpu0_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .pwrdm = { .name = "cpu0_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct clockdomain iva_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "iva_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .pwrdm = { .name = "iva_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .cm_inst = DRA7XX_CM_CORE_IVA_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .wkdep_srcs = iva_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .sleepdep_srcs = iva_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct clockdomain coreaon_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .name = "coreaon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .pwrdm = { .name = "coreaon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct clockdomain ipu1_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .name = "ipu1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .pwrdm = { .name = "ipu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .wkdep_srcs = ipu1_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .sleepdep_srcs = ipu1_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static struct clockdomain ipu2_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .name = "ipu2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .wkdep_srcs = ipu2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .sleepdep_srcs = ipu2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct clockdomain l3init_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "l3init_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pwrdm = { .name = "l3init_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .wkdep_srcs = l3init_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .sleepdep_srcs = l3init_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct clockdomain l4sec_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "l4sec_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pwrdm = { .name = "l4per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .wkdep_srcs = l4sec_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .sleepdep_srcs = l4sec_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct clockdomain l3main1_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "l3main1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct clockdomain vpe_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "vpe_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .pwrdm = { .name = "vpe_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .wkdep_srcs = vpe_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .sleepdep_srcs = vpe_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct clockdomain mpu_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .wkdep_srcs = mpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .sleepdep_srcs = mpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct clockdomain custefuse_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "custefuse_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .pwrdm = { .name = "custefuse_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct clockdomain ipu_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "ipu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .pwrdm = { .name = "ipu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static struct clockdomain mpu1_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .name = "mpu1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .pwrdm = { .name = "cpu1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct clockdomain gmac_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "gmac_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .pwrdm = { .name = "l3init_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .wkdep_srcs = gmac_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .sleepdep_srcs = gmac_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct clockdomain l4cfg_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "l4cfg_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct clockdomain dma_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .name = "dma_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .wkdep_srcs = dma_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .sleepdep_srcs = dma_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct clockdomain rtc_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = "rtc_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .pwrdm = { .name = "rtc_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static struct clockdomain pcie_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "pcie_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .pwrdm = { .name = "l3init_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .wkdep_srcs = pcie_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .sleepdep_srcs = pcie_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static struct clockdomain atl_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "atl_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct clockdomain l3instr_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "l3instr_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct clockdomain dss_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .pwrdm = { .name = "dss_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .cm_inst = DRA7XX_CM_CORE_DSS_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .wkdep_srcs = dss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .sleepdep_srcs = dss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct clockdomain emif_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .name = "emif_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .cm_inst = DRA7XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static struct clockdomain emu_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = "emu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .pwrdm = { .name = "emu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .cm_inst = DRA7XX_PRM_EMU_CM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct clockdomain dsp2_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "dsp2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .pwrdm = { .name = "dsp2_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .wkdep_srcs = dsp2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .sleepdep_srcs = dsp2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static struct clockdomain dsp1_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .name = "dsp1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .pwrdm = { .name = "dsp1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .wkdep_srcs = dsp1_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .sleepdep_srcs = dsp1_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct clockdomain cam_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .name = "cam_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .pwrdm = { .name = "cam_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .cm_inst = DRA7XX_CM_CORE_CAM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .wkdep_srcs = cam_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .sleepdep_srcs = cam_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct clockdomain l4per_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = "l4per_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .pwrdm = { .name = "l4per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static struct clockdomain gpu_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .name = "gpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .pwrdm = { .name = "gpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .prcm_partition = DRA7XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .cm_inst = DRA7XX_CM_CORE_GPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .wkdep_srcs = gpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .sleepdep_srcs = gpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static struct clockdomain eve4_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .name = "eve4_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .pwrdm = { .name = "eve4_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .wkdep_srcs = eve4_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .sleepdep_srcs = eve4_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct clockdomain eve2_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .name = "eve2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .pwrdm = { .name = "eve2_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .wkdep_srcs = eve2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .sleepdep_srcs = eve2_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static struct clockdomain eve3_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "eve3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .pwrdm = { .name = "eve3_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .wkdep_srcs = eve3_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .sleepdep_srcs = eve3_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static struct clockdomain wkupaon_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .name = "wkupaon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pwrdm = { .name = "wkupaon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .prcm_partition = DRA7XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static struct clockdomain eve1_7xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .name = "eve1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .pwrdm = { .name = "eve1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .wkdep_srcs = eve1_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .sleepdep_srcs = eve1_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* As clockdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct clockdomain *clockdomains_dra7xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) &l4per3_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) &l4per2_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) &mpu0_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) &iva_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) &coreaon_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) &ipu1_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) &ipu2_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) &l3init_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) &l4sec_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &l3main1_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) &vpe_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) &mpu_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) &custefuse_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &ipu_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) &mpu1_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) &gmac_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) &l4cfg_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) &dma_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) &rtc_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) &pcie_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) &atl_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) &l3instr_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) &dss_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &emif_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &emu_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) &dsp2_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &dsp1_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &cam_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &l4per_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) &gpu_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) &eve4_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) &eve2_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) &eve3_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) &wkupaon_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) &eve1_7xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) void __init dra7xx_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clkdm_register_platform_funcs(&omap4_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) clkdm_register_clkdms(clockdomains_dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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