^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP54XX Clock domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Abhijit Pagare (abhijitpagare@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cm1_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "cm2_54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "cm-regbits-54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "prm54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "prcm_mpu54xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Static Dependencies for OMAP4 Clock Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct clkdm_dep c2c_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { .clkdm_name = "l3main2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct clkdm_dep cam_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct clkdm_dep dma_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct clkdm_dep dsp_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .clkdm_name = "l3main2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct clkdm_dep dss_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .clkdm_name = "l3main2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct clkdm_dep gpu_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct clkdm_dep ipu_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { .clkdm_name = "dsp_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .clkdm_name = "l3main2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static struct clkdm_dep iva_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct clkdm_dep l3init_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .clkdm_name = "l3main2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct clkdm_dep mpu_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .clkdm_name = "dsp_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .clkdm_name = "emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .clkdm_name = "gpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .clkdm_name = "ipu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .clkdm_name = "iva_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .clkdm_name = "l3init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .clkdm_name = "l3main1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .clkdm_name = "l3main2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .clkdm_name = "l4cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { .clkdm_name = "l4per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .clkdm_name = "l4sec_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .clkdm_name = "wkupaon_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct clockdomain l4sec_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "l4sec_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .wkdep_srcs = l4sec_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .sleepdep_srcs = l4sec_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clockdomain iva_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "iva_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .pwrdm = { .name = "iva_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .cm_inst = OMAP54XX_CM_CORE_IVA_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .clkdm_offs = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .dep_bit = OMAP54XX_IVA_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .wkdep_srcs = iva_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .sleepdep_srcs = iva_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct clockdomain mipiext_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "mipiext_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .clkdm_offs = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .wkdep_srcs = mipiext_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .sleepdep_srcs = mipiext_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct clockdomain l3main2_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "l3main2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .dep_bit = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct clockdomain l3main1_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "l3main1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .dep_bit = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct clockdomain custefuse_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "custefuse_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .pwrdm = { .name = "custefuse_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .cm_inst = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .clkdm_offs = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct clockdomain ipu_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "ipu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .clkdm_offs = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .dep_bit = OMAP54XX_IPU_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .wkdep_srcs = ipu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .sleepdep_srcs = ipu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct clockdomain l4cfg_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "l4cfg_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .dep_bit = OMAP54XX_L4CFG_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct clockdomain abe_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "abe_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .pwrdm = { .name = "abe_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .cm_inst = OMAP54XX_CM_CORE_AON_ABE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .clkdm_offs = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .dep_bit = OMAP54XX_ABE_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct clockdomain dss_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .pwrdm = { .name = "dss_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cm_inst = OMAP54XX_CM_CORE_DSS_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .clkdm_offs = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .dep_bit = OMAP54XX_DSS_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .wkdep_srcs = dss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .sleepdep_srcs = dss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct clockdomain dsp_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .name = "dsp_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .pwrdm = { .name = "dsp_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .cm_inst = OMAP54XX_CM_CORE_AON_DSP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .clkdm_offs = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .dep_bit = OMAP54XX_DSP_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .wkdep_srcs = dsp_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .sleepdep_srcs = dsp_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct clockdomain c2c_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "c2c_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .clkdm_offs = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .wkdep_srcs = c2c_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .sleepdep_srcs = c2c_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static struct clockdomain l4per_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "l4per_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .clkdm_offs = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .dep_bit = OMAP54XX_L4PER_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct clockdomain gpu_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "gpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .pwrdm = { .name = "gpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .cm_inst = OMAP54XX_CM_CORE_GPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .clkdm_offs = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .dep_bit = OMAP54XX_GPU_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .wkdep_srcs = gpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .sleepdep_srcs = gpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct clockdomain wkupaon_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "wkupaon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .pwrdm = { .name = "wkupaon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .prcm_partition = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .cm_inst = OMAP54XX_PRM_WKUPAON_CM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .clkdm_offs = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .dep_bit = OMAP54XX_WKUPAON_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct clockdomain mpu0_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "mpu0_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .pwrdm = { .name = "cpu0_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .cm_inst = OMAP54XX_PRCM_MPU_CM_C0_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct clockdomain mpu1_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "mpu1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .pwrdm = { .name = "cpu1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .prcm_partition = OMAP54XX_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .cm_inst = OMAP54XX_PRCM_MPU_CM_C1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .clkdm_offs = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct clockdomain coreaon_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "coreaon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .pwrdm = { .name = "coreaon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .cm_inst = OMAP54XX_CM_CORE_COREAON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .clkdm_offs = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct clockdomain mpu_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .prcm_partition = OMAP54XX_CM_CORE_AON_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .cm_inst = OMAP54XX_CM_CORE_AON_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .clkdm_offs = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .wkdep_srcs = mpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .sleepdep_srcs = mpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct clockdomain l3init_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "l3init_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .pwrdm = { .name = "l3init_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .cm_inst = OMAP54XX_CM_CORE_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .clkdm_offs = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .dep_bit = OMAP54XX_L3INIT_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .wkdep_srcs = l3init_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .sleepdep_srcs = l3init_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct clockdomain dma_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "dma_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .clkdm_offs = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .wkdep_srcs = dma_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .sleepdep_srcs = dma_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct clockdomain l3instr_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "l3instr_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .clkdm_offs = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static struct clockdomain emif_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "emif_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .cm_inst = OMAP54XX_CM_CORE_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .clkdm_offs = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .dep_bit = OMAP54XX_EMIF_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct clockdomain emu_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "emu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .pwrdm = { .name = "emu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .prcm_partition = OMAP54XX_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .cm_inst = OMAP54XX_PRM_EMU_CM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .clkdm_offs = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clockdomain cam_54xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .name = "cam_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .pwrdm = { .name = "cam_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .prcm_partition = OMAP54XX_CM_CORE_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .cm_inst = OMAP54XX_CM_CORE_CAM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .clkdm_offs = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .wkdep_srcs = cam_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .sleepdep_srcs = cam_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* As clockdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static struct clockdomain *clockdomains_omap54xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &l4sec_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &iva_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &mipiext_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) &l3main2_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) &l3main1_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &custefuse_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &ipu_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) &l4cfg_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &abe_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &dss_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &dsp_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &c2c_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &l4per_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &gpu_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &wkupaon_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) &mpu0_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &mpu1_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) &coreaon_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &mpu_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &l3init_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &dma_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &l3instr_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &emif_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &emu_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &cam_54xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void __init omap54xx_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clkdm_register_platform_funcs(&omap4_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) clkdm_register_clkdms(clockdomains_omap54xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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