^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP4 Clock domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Abhijit Pagare (abhijitpagare@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Benoit Cousson (b-cousson@ti.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Paul Walmsley (paul@pwsan.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file is automatically generated from the OMAP hardware databases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * We respectfully ask that any modifications to this file be coordinated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * with the public linux-omap@vger.kernel.org mailing list and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * authors above to ensure that the autogeneration scripts are kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * up-to-date with the file contents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "cm1_44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "cm2_44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "cm-regbits-44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "prm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "prcm_mpu44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Static Dependencies for OMAP4 Clock Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct clkdm_dep d2d_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { .clkdm_name = "l3_2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { .clkdm_name = "l3_init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .clkdm_name = "l4_cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct clkdm_dep ducati_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .clkdm_name = "l3_2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .clkdm_name = "l3_dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .clkdm_name = "l3_gfx_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .clkdm_name = "l3_init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .clkdm_name = "l4_cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .clkdm_name = "l4_secure_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { .clkdm_name = "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .clkdm_name = "tesla_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct clkdm_dep iss_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .clkdm_name = "ducati_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .clkdm_name = "l3_dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .clkdm_name = "l3_init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .clkdm_name = "l4_cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { .clkdm_name = "l4_secure_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .clkdm_name = "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .clkdm_name = "l3_2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { .clkdm_name = "l4_cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .clkdm_name = "l4_secure_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .clkdm_name = "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static struct clkdm_dep mpu_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .clkdm_name = "ducati_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .clkdm_name = "l3_2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .clkdm_name = "l3_dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .clkdm_name = "l3_gfx_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .clkdm_name = "l3_init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .clkdm_name = "l4_cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { .clkdm_name = "l4_secure_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { .clkdm_name = "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .clkdm_name = "tesla_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clkdm_dep tesla_wkup_sleep_deps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .clkdm_name = "abe_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .clkdm_name = "ivahd_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .clkdm_name = "l3_1_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .clkdm_name = "l3_2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .clkdm_name = "l3_emif_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .clkdm_name = "l3_init_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .clkdm_name = "l4_cfg_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .clkdm_name = "l4_per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .clkdm_name = "l4_wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clockdomain l4_cefuse_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "l4_cefuse_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pwrdm = { .name = "cefuse_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .cm_inst = OMAP4430_CM2_CEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct clockdomain l4_cfg_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .name = "l4_cfg_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct clockdomain tesla_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "tesla_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pwrdm = { .name = "tesla_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .prcm_partition = OMAP4430_CM1_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .cm_inst = OMAP4430_CM1_TESLA_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .wkdep_srcs = tesla_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .sleepdep_srcs = tesla_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clockdomain l3_gfx_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "l3_gfx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .pwrdm = { .name = "gfx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .cm_inst = OMAP4430_CM2_GFX_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .wkdep_srcs = l3_gfx_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clockdomain ivahd_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "ivahd_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .pwrdm = { .name = "ivahd_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .cm_inst = OMAP4430_CM2_IVAHD_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .wkdep_srcs = ivahd_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .sleepdep_srcs = ivahd_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct clockdomain l4_secure_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "l4_secure_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .pwrdm = { .name = "l4per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .cm_inst = OMAP4430_CM2_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .wkdep_srcs = l4_secure_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .sleepdep_srcs = l4_secure_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct clockdomain l4_per_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "l4_per_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .pwrdm = { .name = "l4per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .cm_inst = OMAP4430_CM2_L4PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct clockdomain abe_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "abe_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .pwrdm = { .name = "abe_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .prcm_partition = OMAP4430_CM1_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .cm_inst = OMAP4430_CM1_ABE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct clockdomain l3_instr_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "l3_instr_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct clockdomain l3_init_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "l3_init_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pwrdm = { .name = "l3init_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .cm_inst = OMAP4430_CM2_L3INIT_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .wkdep_srcs = l3_init_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .sleepdep_srcs = l3_init_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct clockdomain d2d_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "d2d_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .wkdep_srcs = d2d_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .sleepdep_srcs = d2d_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct clockdomain mpu0_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "mpu0_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .pwrdm = { .name = "cpu0_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct clockdomain mpu1_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "mpu1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .pwrdm = { .name = "cpu1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct clockdomain l3_emif_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "l3_emif_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct clockdomain l4_ao_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .name = "l4_ao_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .pwrdm = { .name = "always_on_core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct clockdomain ducati_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = "ducati_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .wkdep_srcs = ducati_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .sleepdep_srcs = ducati_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct clockdomain mpu_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "mpuss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .prcm_partition = OMAP4430_CM1_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .cm_inst = OMAP4430_CM1_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .wkdep_srcs = mpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .sleepdep_srcs = mpu_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct clockdomain l3_2_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .name = "l3_2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct clockdomain l3_1_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "l3_1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct clockdomain iss_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "iss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .pwrdm = { .name = "cam_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .cm_inst = OMAP4430_CM2_CAM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .wkdep_srcs = iss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .sleepdep_srcs = iss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct clockdomain l3_dss_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "l3_dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .pwrdm = { .name = "dss_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .cm_inst = OMAP4430_CM2_DSS_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .wkdep_srcs = l3_dss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .sleepdep_srcs = l3_dss_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct clockdomain l4_wkup_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .name = "l4_wkup_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct clockdomain emu_sys_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "emu_sys_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .pwrdm = { .name = "emu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .prcm_partition = OMAP4430_PRM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .cm_inst = OMAP4430_PRM_EMU_CM_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CLKDM_MISSING_IDLE_REPORTING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct clockdomain l3_dma_44xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "l3_dma_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .prcm_partition = OMAP4430_CM2_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .cm_inst = OMAP4430_CM2_CORE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .wkdep_srcs = l3_dma_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .sleepdep_srcs = l3_dma_wkup_sleep_deps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* As clockdomains are added or removed above, this list must also be changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct clockdomain *clockdomains_omap44xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) &l4_cefuse_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &l4_cfg_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &tesla_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) &l3_gfx_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) &ivahd_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) &l4_secure_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) &l4_per_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) &abe_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &l3_instr_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &l3_init_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &d2d_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) &mpu0_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) &mpu1_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) &l3_emif_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &l4_ao_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &ducati_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &mpu_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) &l3_2_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &l3_1_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &iss_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) &l3_dss_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) &l4_wkup_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) &emu_sys_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) &l3_dma_44xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void __init omap44xx_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clkdm_register_platform_funcs(&omap4_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) clkdm_register_clkdms(clockdomains_omap44xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags