^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AM43xx Clock domains framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "prcm44xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "prcm43xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static struct clockdomain l4_cefuse_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .name = "l4_cefuse_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .pwrdm = { .name = "cefuse_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .cm_inst = AM43XX_CM_CEFUSE_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .clkdm_offs = AM43XX_CM_CEFUSE_CEFUSE_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct clockdomain mpu_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .cm_inst = AM43XX_CM_MPU_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .clkdm_offs = AM43XX_CM_MPU_MPU_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct clockdomain l4ls_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = "l4ls_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .clkdm_offs = AM43XX_CM_PER_L4LS_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct clockdomain tamper_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .name = "tamper_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .pwrdm = { .name = "tamper_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .cm_inst = AM43XX_CM_TAMPER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .clkdm_offs = AM43XX_CM_TAMPER_TAMPER_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct clockdomain l4_rtc_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = "l4_rtc_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .pwrdm = { .name = "rtc_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .cm_inst = AM43XX_CM_RTC_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .clkdm_offs = AM43XX_CM_RTC_RTC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct clockdomain pruss_ocp_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .name = "pruss_ocp_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .clkdm_offs = AM43XX_CM_PER_ICSS_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct clockdomain ocpwp_l3_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .name = "ocpwp_l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .clkdm_offs = AM43XX_CM_PER_OCPWP_L3_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clockdomain l3s_tsc_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = "l3s_tsc_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .cm_inst = AM43XX_CM_WKUP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .clkdm_offs = AM43XX_CM_WKUP_L3S_TSC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct clockdomain lcdc_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "lcdc_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct clockdomain dss_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = "dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .clkdm_offs = AM43XX_CM_PER_DSS_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clockdomain l3_aon_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "l3_aon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .cm_inst = AM43XX_CM_WKUP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .clkdm_offs = AM43XX_CM_WKUP_L3_AON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct clockdomain emif_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "emif_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .clkdm_offs = AM43XX_CM_PER_EMIF_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct clockdomain l4_wkup_aon_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "l4_wkup_aon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .cm_inst = AM43XX_CM_WKUP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .clkdm_offs = AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct clockdomain l3_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .clkdm_offs = AM43XX_CM_PER_L3_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clockdomain l4_wkup_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "l4_wkup_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .cm_inst = AM43XX_CM_WKUP_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .clkdm_offs = AM43XX_CM_WKUP_WKUP_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct clockdomain cpsw_125mhz_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "cpsw_125mhz_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .clkdm_offs = AM43XX_CM_PER_CPSW_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct clockdomain gfx_l3_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "gfx_l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .pwrdm = { .name = "gfx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .cm_inst = AM43XX_CM_GFX_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .clkdm_offs = AM43XX_CM_GFX_GFX_L3_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct clockdomain l3s_43xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "l3s_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .prcm_partition = AM43XX_CM_PARTITION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .cm_inst = AM43XX_CM_PER_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .clkdm_offs = AM43XX_CM_PER_L3S_CDOFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct clockdomain *clockdomains_am43xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) &l4_cefuse_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &mpu_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &l4ls_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) &tamper_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &l4_rtc_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &pruss_ocp_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &ocpwp_l3_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &l3s_tsc_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &lcdc_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &dss_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &l3_aon_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &emif_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &l4_wkup_aon_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) &l3_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &l4_wkup_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &cpsw_125mhz_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &gfx_l3_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &l3s_43xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) void __init am43xx_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clkdm_register_platform_funcs(&am43xx_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clkdm_register_clkdms(clockdomains_am43xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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