^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP3xxx clockdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2011 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley, Jouni Högander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file contains clockdomains and clockdomain wakeup/sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * dependencies for the OMAP3xxx chips. Some notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * A useful validation rule for struct clockdomain: Any clockdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * referenced by a wkdep_srcs or sleepdep_srcs array must have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * software-controllable dependencies. Non-software-controllable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * dependencies do exist, but they are not encoded below (yet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The overly-specific dep_bit names are due to a bit name collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * value are the same for all powerdomains: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * sanity check?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * To-Do List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * -> Port the Sleep/Wakeup dependencies for the domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * from the Power domain framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "cm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "prm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Clockdomain dependencies for wkdeps/sleepdeps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * XXX Hardware dependencies (e.g., dependencies that cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * changed in software) are not included here yet, but should be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* OMAP3-specific possible dependencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct clkdm_dep per_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static struct clkdm_dep per_am35x_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clkdm_dep usbhost_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct clkdm_dep usbhost_am35x_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct clkdm_dep mpu_3xxx_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { .clkdm_name = "per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct clkdm_dep mpu_am35x_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .clkdm_name = "per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct clkdm_dep iva2_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .clkdm_name = "dss_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .clkdm_name = "per_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct clkdm_dep cam_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct clkdm_dep dss_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct clkdm_dep dss_am35x_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 3430: PM_WKDEP_NEON: MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct clkdm_dep neon_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Sleep dependency source arrays for OMAP3-specific clkdms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct clkdm_dep dss_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct clkdm_dep dss_am35x_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct clkdm_dep per_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct clkdm_dep per_am35x_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct clkdm_dep usbhost_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .clkdm_name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* 3430: CM_SLEEPDEP_CAM: MPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct clkdm_dep cam_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 3430ES1: CM_SLEEPDEP_GFX: MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 3430ES2: CM_SLEEPDEP_SGX: MPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * These can share data since they will never be present simultaneously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * on the same device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static struct clkdm_dep gfx_sgx_sleepdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * OMAP3 clockdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct clockdomain mpu_3xxx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .dep_bit = OMAP3430_EN_MPU_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .wkdep_srcs = mpu_3xxx_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct clockdomain mpu_am35x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .dep_bit = OMAP3430_EN_MPU_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .wkdep_srcs = mpu_am35x_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static struct clockdomain neon_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "neon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .pwrdm = { .name = "neon_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .wkdep_srcs = neon_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct clockdomain iva2_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "iva2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pwrdm = { .name = "iva2_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .wkdep_srcs = iva2_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct clockdomain gfx_3430es1_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "gfx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .pwrdm = { .name = "gfx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .sleepdep_srcs = gfx_sgx_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct clockdomain sgx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "sgx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .pwrdm = { .name = "sgx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .wkdep_srcs = gfx_sgx_3xxx_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .sleepdep_srcs = gfx_sgx_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct clockdomain sgx_am35x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "sgx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .pwrdm = { .name = "sgx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .wkdep_srcs = gfx_sgx_am35x_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .sleepdep_srcs = gfx_sgx_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * then that information was removed from the 34xx ES2+ TRM. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * unclear whether the core is still there, but the clockdomain logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * is there, and must be programmed to an appropriate state if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * CORE clockdomain is to become inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct clockdomain d2d_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "d2d_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * XXX add usecounting for clkdm dependencies, otherwise the presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * could cause trouble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct clockdomain core_l3_3xxx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "core_l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .dep_bit = OMAP3430_EN_CORE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * XXX add usecounting for clkdm dependencies, otherwise the presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * could cause trouble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct clockdomain core_l4_3xxx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "core_l4_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .dep_bit = OMAP3430_EN_CORE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Another case of bit name collisions between several registers: EN_DSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct clockdomain dss_3xxx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = "dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .pwrdm = { .name = "dss_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .wkdep_srcs = dss_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .sleepdep_srcs = dss_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct clockdomain dss_am35x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .name = "dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .pwrdm = { .name = "dss_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .wkdep_srcs = dss_am35x_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .sleepdep_srcs = dss_am35x_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct clockdomain cam_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = "cam_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .pwrdm = { .name = "cam_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .wkdep_srcs = cam_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .sleepdep_srcs = cam_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct clockdomain usbhost_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "usbhost_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .pwrdm = { .name = "usbhost_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .wkdep_srcs = usbhost_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .sleepdep_srcs = usbhost_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct clockdomain usbhost_am35x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "usbhost_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .wkdep_srcs = usbhost_am35x_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .sleepdep_srcs = usbhost_am35x_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct clockdomain per_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .name = "per_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .dep_bit = OMAP3430_EN_PER_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .wkdep_srcs = per_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .sleepdep_srcs = per_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct clockdomain per_am35x_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "per_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .dep_bit = OMAP3430_EN_PER_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .wkdep_srcs = per_am35x_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .sleepdep_srcs = per_am35x_sleepdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct clockdomain emu_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "emu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .pwrdm = { .name = "emu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .flags = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CLKDM_MISSING_IDLE_REPORTING),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct clockdomain dpll1_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "dpll1_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pwrdm = { .name = "dpll1_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct clockdomain dpll2_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "dpll2_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .pwrdm = { .name = "dpll2_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct clockdomain dpll3_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .name = "dpll3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .pwrdm = { .name = "dpll3_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clockdomain dpll4_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .name = "dpll4_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .pwrdm = { .name = "dpll4_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct clockdomain dpll5_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .name = "dpll5_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .pwrdm = { .name = "dpll5_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Clockdomain hwsup dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct clkdm_autodep clkdm_autodeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .clkdm = { .name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .clkdm = { .name = "iva2_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .clkdm = { .name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static struct clkdm_autodep clkdm_am35x_autodeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .clkdm = { .name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .clkdm = { .name = NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct clockdomain *clockdomains_common[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &wkup_common_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &neon_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &core_l3_3xxx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) &core_l4_3xxx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &emu_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) &dpll1_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) &dpll3_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &dpll4_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct clockdomain *clockdomains_omap3430[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) &mpu_3xxx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &iva2_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &d2d_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) &dss_3xxx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &cam_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &per_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &dpll2_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) &gfx_3430es1_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &sgx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &dpll5_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &usbhost_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct clockdomain *clockdomains_am35x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &mpu_am35x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &sgx_am35x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) &dss_am35x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &per_am35x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &usbhost_am35x_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) &dpll5_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void __init omap3xxx_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct clockdomain **sc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) clkdm_register_platform_funcs(&omap3_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) clkdm_register_clkdms(clockdomains_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rev = omap_rev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clkdm_register_clkdms(clockdomains_am35x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clkdm_register_autodeps(clkdm_am35x_autodeps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clkdm_register_clkdms(clockdomains_omap3430);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) sc = (rev == OMAP3430_REV_ES1_0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clkdm_register_clkdms(sc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clkdm_register_autodeps(clkdm_autodeps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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