^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AM33XX Clock Domain data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Vaibhav Hiremath <hvaibhav@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cm33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "cm-regbits-33xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct clockdomain l4ls_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .name = "l4ls_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct clockdomain l3s_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = "l3s_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct clockdomain l4fw_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .name = "l4fw_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct clockdomain l3_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct clockdomain l4hs_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = "l4hs_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct clockdomain ocpwp_l3_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .name = "ocpwp_l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct clockdomain pruss_ocp_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "pruss_ocp_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "cpsw_125mhz_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clockdomain lcdc_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = "lcdc_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct clockdomain clk_24mhz_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "clk_24mhz_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pwrdm = { .name = "per_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .cm_inst = AM33XX_CM_PER_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clockdomain l4_wkup_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "l4_wkup_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .cm_inst = AM33XX_CM_WKUP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct clockdomain l3_aon_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "l3_aon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .cm_inst = AM33XX_CM_WKUP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .name = "l4_wkup_aon_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .pwrdm = { .name = "wkup_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .cm_inst = AM33XX_CM_WKUP_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct clockdomain mpu_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .cm_inst = AM33XX_CM_MPU_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct clockdomain l4_rtc_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "l4_rtc_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .pwrdm = { .name = "rtc_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .cm_inst = AM33XX_CM_RTC_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct clockdomain gfx_l3_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "gfx_l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .pwrdm = { .name = "gfx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .cm_inst = AM33XX_CM_GFX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "gfx_l4ls_gfx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pwrdm = { .name = "gfx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .cm_inst = AM33XX_CM_GFX_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct clockdomain l4_cefuse_am33xx_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "l4_cefuse_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .pwrdm = { .name = "cefuse_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .cm_inst = AM33XX_CM_CEFUSE_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .flags = CLKDM_CAN_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct clockdomain *clockdomains_am33xx[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) &l4ls_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &l3s_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) &l4fw_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) &l3_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) &l4hs_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &ocpwp_l3_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) &pruss_ocp_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) &cpsw_125mhz_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &lcdc_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &clk_24mhz_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) &l4_wkup_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &l3_aon_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &l4_wkup_aon_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &mpu_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &l4_rtc_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &gfx_l3_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &gfx_l4ls_gfx_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &l4_cefuse_am33xx_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __init am33xx_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clkdm_register_platform_funcs(&am33xx_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) clkdm_register_clkdms(clockdomains_am33xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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