^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2xxx clockdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paul Walmsley, Jouni Högander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file contains clockdomains and clockdomain wakeup dependencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * for OMAP2xxx chips. Some notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * A useful validation rule for struct clockdomain: Any clockdomain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * referenced by a wkdep_srcs must have a dep_bit assigned. So
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * wkdep_srcs are really just software-controllable dependencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Non-software-controllable dependencies do exist, but they are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * encoded below (yet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 24xx does not support programmable sleep dependencies (SLEEPDEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The overly-specific dep_bit names are due to a bit name collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * value are the same for all powerdomains: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * sanity check?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * To-Do List
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * -> Port the Sleep/Wakeup dependencies for the domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * from the Power domain framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "prm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "cm2xxx_3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "cm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "prm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Clockdomain dependencies for wkdeps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * XXX Hardware dependencies (e.g., dependencies that cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * changed in software) are not included here yet, but should be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Wakeup dependency source arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* 2430-specific possible wakeup dependencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 2430 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP, MDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct clkdm_dep core_2430_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .clkdm_name = "dsp_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .clkdm_name = "gfx_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { .clkdm_name = "mdm_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* 2430 PM_WKDEP_MPU: CORE, DSP, WKUP, MDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct clkdm_dep mpu_2430_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .clkdm_name = "dsp_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { .clkdm_name = "mdm_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clkdm_dep mdm_2430_wkdeps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .clkdm_name = "core_l3_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .clkdm_name = "core_l4_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .clkdm_name = "mpu_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { .clkdm_name = "wkup_clkdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 2430-only clockdomains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct clockdomain mpu_2430_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "mpu_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .pwrdm = { .name = "mpu_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .wkdep_srcs = mpu_2430_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Another case of bit name collisions between several registers: EN_MDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct clockdomain mdm_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "mdm_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pwrdm = { .name = "mdm_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .wkdep_srcs = mdm_2430_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct clockdomain dsp_2430_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "dsp_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pwrdm = { .name = "dsp_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .wkdep_srcs = dsp_24xx_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clockdomain gfx_2430_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "gfx_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .pwrdm = { .name = "gfx_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .flags = CLKDM_CAN_HWSUP_SWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .wkdep_srcs = gfx_24xx_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * XXX add usecounting for clkdm dependencies, otherwise the presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * could cause trouble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct clockdomain core_l3_2430_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "core_l3_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .dep_bit = OMAP24XX_EN_CORE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .wkdep_srcs = core_2430_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * XXX add usecounting for clkdm dependencies, otherwise the presence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * could cause trouble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct clockdomain core_l4_2430_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "core_l4_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .dep_bit = OMAP24XX_EN_CORE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .wkdep_srcs = core_2430_wkdeps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct clockdomain dss_2430_clkdm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "dss_clkdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pwrdm = { .name = "core_pwrdm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .flags = CLKDM_CAN_HWSUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct clockdomain *clockdomains_omap243x[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &wkup_common_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) &mpu_2430_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &mdm_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &dsp_2430_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) &gfx_2430_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &core_l3_2430_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &core_l4_2430_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) &dss_2430_clkdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void __init omap243x_clockdomains_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!cpu_is_omap243x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clkdm_register_platform_funcs(&omap2_clkdm_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clkdm_register_clkdms(clockdomains_omap243x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) clkdm_complete_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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