Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP2 clock function prototypes and macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2005-2010 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2004-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ARCH_ARM_MACH_OMAP2_CLOCK2XXX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 				     unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			    unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			       unsigned long *parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				      unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 				   unsigned long parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long omap2xxx_clk_get_core_rate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 omap2xxx_get_sysclkdiv(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void omap2xxx_clk_prepare_for_reboot(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void omap2xxx_clkt_vps_check_bootloader_rates(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void omap2xxx_clkt_vps_late_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef CONFIG_SOC_OMAP2420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int omap2420_clk_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define omap2420_clk_init()	do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifdef CONFIG_SOC_OMAP2430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int omap2430_clk_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define omap2430_clk_init()	do { } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern struct clk_hw *dclk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif