^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap2/clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2009 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contacts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __ARCH_ARM_MACH_OMAP2_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk/ti.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* struct clksel_rate.flags possibilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RATE_IN_242X (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RATE_IN_243X (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RATE_IN_36XX (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RATE_IN_4430 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RATE_IN_TI816X (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RATE_IN_4460 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RATE_IN_AM33XX (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RATE_IN_TI814X (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CORE_CLK_SRC_32K 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CORE_CLK_SRC_DPLL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CORE_CLK_SRC_DPLL_X2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP2XXX_EN_DPLL_LOCKED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OMAP3XXX_EN_DPLL_LOCKED 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OMAP4XXX_EN_DPLL_LOCKED 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern struct ti_clk_ll_ops omap_clk_ll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern u16 cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern const struct clkops clkops_omap2_dflt_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern const struct clkops clkops_omap2_dflt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern struct clk_functions omap2_clk_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int __init omap2_clk_setup_ll_ops(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void __init ti_clk_init_features(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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