^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap2/clock.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005-2008 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contacts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Richard Woodruff <r-woodruff2@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <trace/events/power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "clockdomain.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "cm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "cm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "cm3xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "cm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "cm-regbits-34xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OMAP3430_DPLL_FINT_BAND1_MIN 750000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * From device data manual section 4.3 "DPLL and DLL Specifications".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OMAP3PLUS_DPLL_FINT_MIN 32000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OMAP3PLUS_DPLL_FINT_MAX 52000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct ti_clk_ll_ops omap_clk_ll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .clkdm_clk_enable = clkdm_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .clkdm_clk_disable = clkdm_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .clkdm_lookup = clkdm_lookup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .cm_wait_module_ready = omap_cm_wait_module_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .cm_split_idlest_reg = cm_split_idlest_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * omap2_clk_setup_ll_ops - setup clock driver low-level ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Sets up clock driver low-level platform ops. These are needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * for register accesses and various other misc platform operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Returns 0 on success, -EBUSY if low level ops have been registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int __init omap2_clk_setup_ll_ops(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * OMAP2+ specific clock functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * ti_clk_init_features - init clock features struct for the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Initializes the clock features struct based on the SoC type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void __init ti_clk_init_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ti_clk_features features = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Fint setup for DPLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (cpu_is_omap3430()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Bypass value setup for DPLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (cpu_is_omap24xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) features.dpll_bypass_vals |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else if (cpu_is_omap34xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) features.dpll_bypass_vals |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) soc_is_omap54xx() || soc_is_dra7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) features.dpll_bypass_vals |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Jitter correction only available on OMAP343X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (cpu_is_omap343x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (omap_type() == OMAP2_DEVICE_TYPE_GP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) features.flags |= TI_CLK_DEVICE_TYPE_GP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Idlest value for interface clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 34xx reverses this, just to keep us on our toes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * AM35xx uses both, depending on the module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (cpu_is_omap24xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) else if (cpu_is_omap34xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (omap_rev() == OMAP3430_REV_ES1_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Errata I810 for omap5 / dra7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (soc_is_omap54xx() || soc_is_dra7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) features.flags |= TI_CLK_ERRATA_I810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ti_clk_setup_features(&features);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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