Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP2-specific DPLL control functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2011 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cm2xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cm-regbits-24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Private functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * _allow_idle - enable DPLL autoidle bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * @clk: struct clk * of the DPLL to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Enable DPLL automatic idle control.  The DPLL will enter low-power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * stop when its downstream clocks are gated.  No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * instead.  Add some mechanism to optionally enter this mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void _allow_idle(struct clk_hw_omap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	if (!clk || !clk->dpll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	omap2xxx_cm_set_dpll_auto_low_power_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * _deny_idle - prevent DPLL from automatically idling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * @clk: struct clk * of the DPLL to operate on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * Disable DPLL automatic idle control.  No return value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void _deny_idle(struct clk_hw_omap *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	if (!clk || !clk->dpll_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	omap2xxx_cm_set_dpll_disable_autoidle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Public data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.allow_idle	= _allow_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.deny_idle	= _deny_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };