Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-omap2/board-n8x0.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2005-2009 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Juha Yrjola <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Modified from mach-omap2/board-generic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/usb/musb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/platform_data/spi-omap2-mcspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_data/mmc-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/mfd/menelaus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <sound/tlv320aic3x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "common-board-devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TUSB6010_ASYNC_CS	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TUSB6010_SYNC_CS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TUSB6010_GPIO_INT	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TUSB6010_GPIO_ENABLE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TUSB6010_DMACHAN	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define NOKIA_N810_WIMAX	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define NOKIA_N810		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define NOKIA_N800		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static u32 board_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define board_is_n800()		(board_caps & NOKIA_N800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define board_is_n810()		(board_caps & NOKIA_N810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define board_is_n810_wimax()	(board_caps & NOKIA_N810_WIMAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static void board_check_revision(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (of_machine_is_compatible("nokia,n800"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		board_caps = NOKIA_N800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	else if (of_machine_is_compatible("nokia,n810"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		board_caps = NOKIA_N810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	else if (of_machine_is_compatible("nokia,n810-wimax"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		board_caps = NOKIA_N810_WIMAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (!board_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		pr_err("Unknown board\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * 1.5 V voltage regulators of PM companion chip. Companion chip will then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * provide then PGOOD signal to TUSB6010 which will release it from reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int tusb_set_power(int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int i, retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		gpio_set_value(TUSB6010_GPIO_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		/* Wait until TUSB6010 pulls INT pin down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		i = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		while (i && gpio_get_value(TUSB6010_GPIO_INT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			i--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			printk(KERN_ERR "tusb: powerup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		gpio_set_value(TUSB6010_GPIO_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static struct musb_hdrc_config musb_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.multipoint	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.dyn_fifo	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.num_eps	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.ram_bits	= 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct musb_hdrc_platform_data tusb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.mode		= MUSB_OTG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.set_power	= tusb_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.min_power	= 25,	/* x2 = 50 mA drawn from VBUS as peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.power		= 100,	/* Max 100 mA VBUS for host mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.config		= &musb_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void __init n8x0_usb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	static const char announce[] __initconst = KERN_INFO "TUSB 6010\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/* PM companion chip power control pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ret = gpio_request_one(TUSB6010_GPIO_ENABLE, GPIOF_OUT_INIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			       "TUSB6010 enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		printk(KERN_ERR "Could not get TUSB power GPIO%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		       TUSB6010_GPIO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	tusb_set_power(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					TUSB6010_ASYNC_CS, TUSB6010_SYNC_CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 					TUSB6010_GPIO_INT, TUSB6010_DMACHAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	printk(announce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	gpio_free(TUSB6010_GPIO_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void __init n8x0_usb_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /*CONFIG_USB_MUSB_TUSB6010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct omap2_mcspi_device_config p54spi_mcspi_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.turbo_mode	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct spi_board_info n800_spi_board_info[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.modalias	= "p54spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.bus_num	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.chip_select	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.max_speed_hz   = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.controller_data = &p54spi_mcspi_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #if defined(CONFIG_MENELAUS) && IS_ENABLED(CONFIG_MMC_OMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * On both N800 and N810, only the first of the two MMC controllers is in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * The two MMC slots are multiplexed via Menelaus companion chip over I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * On N800, both slots are powered via Menelaus. On N810, only one of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * slots is powered via Menelaus. The N810 EMMC is powered via GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * VMMC				slot 1 on both N800 and N810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * VDCDC3_APE and VMCS2_APE	slot 2 on N800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * GPIO23 and GPIO9		slot 2 EMMC on N810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define N8X0_SLOT_SWITCH_GPIO	96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define N810_EMMC_VSD_GPIO	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define N810_EMMC_VIO_GPIO	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int slot1_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int slot2_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct device *mmc_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int n8x0_mmc_switch_slot(struct device *dev, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef CONFIG_MMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	dev_dbg(dev, "Choose slot %d\n", slot + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	gpio_set_value(N8X0_SLOT_SWITCH_GPIO, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int n8x0_mmc_set_power_menelaus(struct device *dev, int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 					int power_on, int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_MMC_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		power_on ? "on" : "off", vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (slot == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (!power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			return menelaus_set_vmmc(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		switch (1 << vdd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		case MMC_VDD_33_34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		case MMC_VDD_32_33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		case MMC_VDD_31_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			mV = 3100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		case MMC_VDD_30_31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			mV = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		case MMC_VDD_28_29:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			mV = 2800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		case MMC_VDD_165_195:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			mV = 1850;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		return menelaus_set_vmmc(mV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		if (!power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			return menelaus_set_vdcdc(3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		switch (1 << vdd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		case MMC_VDD_33_34:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		case MMC_VDD_32_33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			mV = 3300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		case MMC_VDD_30_31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		case MMC_VDD_29_30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			mV = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		case MMC_VDD_28_29:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		case MMC_VDD_27_28:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			mV = 2800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		case MMC_VDD_24_25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		case MMC_VDD_23_24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			mV = 2400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		case MMC_VDD_22_23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		case MMC_VDD_21_22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			mV = 2200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		case MMC_VDD_20_21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			mV = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		case MMC_VDD_165_195:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			mV = 1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return menelaus_set_vdcdc(3, mV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void n810_set_power_emmc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 					 int power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	dev_dbg(dev, "Set EMMC power %s\n", power_on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (power_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		gpio_set_value(N810_EMMC_VSD_GPIO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		gpio_set_value(N810_EMMC_VIO_GPIO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		gpio_set_value(N810_EMMC_VIO_GPIO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		gpio_set_value(N810_EMMC_VSD_GPIO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int n8x0_mmc_set_power(struct device *dev, int slot, int power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			      int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (board_is_n800() || slot == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return n8x0_mmc_set_power_menelaus(dev, slot, power_on, vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	n810_set_power_emmc(dev, power_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int n8x0_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	dev_dbg(dev, "Set slot %d bus mode %s\n", slot + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	BUG_ON(slot != 0 && slot != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	slot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	switch (bus_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	case MMC_BUSMODE_OPENDRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		r = menelaus_set_mmc_opendrain(slot, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	case MMC_BUSMODE_PUSHPULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		r = menelaus_set_mmc_opendrain(slot, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (r != 0 && printk_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		dev_err(dev, "MMC: unable to set bus mode for slot %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int n8x0_mmc_get_cover_state(struct device *dev, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	slot++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	BUG_ON(slot != 1 && slot != 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (slot == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return slot1_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return slot2_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void n8x0_mmc_callback(void *data, u8 card_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifdef CONFIG_MMC_OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	int bit, *openp, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (board_is_n800()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		bit = 1 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		openp = &slot2_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		openp = &slot1_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (card_mask & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		*openp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		*openp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	omap_mmc_notify_cover_event(mmc_device, index, *openp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	pr_warn("MMC: notify cover event not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int n8x0_mmc_late_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	int r, bit, *openp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	int vs2sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	mmc_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	r = menelaus_set_slot_sel(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (board_is_n800())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		vs2sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		vs2sel = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	r = menelaus_set_mmc_slot(2, 0, vs2sel, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	n8x0_mmc_set_power(dev, 0, MMC_POWER_ON, 16); /* MMC_VDD_28_29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	n8x0_mmc_set_power(dev, 1, MMC_POWER_ON, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	r = menelaus_set_mmc_slot(1, 1, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	r = menelaus_set_mmc_slot(2, 1, vs2sel, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	r = menelaus_get_slot_pin_states();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (r < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (board_is_n800()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		bit = 1 << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		openp = &slot2_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		openp = &slot1_cover_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		slot2_cover_open = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	/* All slot pin bits seem to be inversed until first switch change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	if (r == 0xf || r == (0xf & ~bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		r = ~r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (r & bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		*openp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		*openp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	r = menelaus_register_mmc_callback(n8x0_mmc_callback, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void n8x0_mmc_shutdown(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	int vs2sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (board_is_n800())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		vs2sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		vs2sel = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	menelaus_set_mmc_slot(1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	menelaus_set_mmc_slot(2, 0, vs2sel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void n8x0_mmc_cleanup(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	menelaus_unregister_mmc_callback();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	gpio_free(N8X0_SLOT_SWITCH_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (board_is_n810()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		gpio_free(N810_EMMC_VSD_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		gpio_free(N810_EMMC_VIO_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)  * MMC controller1 has two slots that are multiplexed via I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)  * MMC controller2 is not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct omap_mmc_platform_data mmc1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.nr_slots			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.switch_slot			= n8x0_mmc_switch_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.init				= n8x0_mmc_late_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.cleanup			= n8x0_mmc_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.shutdown			= n8x0_mmc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.max_freq			= 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.slots[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.wires			= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.set_power		= n8x0_mmc_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.set_bus_mode		= n8x0_mmc_set_bus_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.get_cover_state	= n8x0_mmc_get_cover_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.ocr_mask		= MMC_VDD_165_195 | MMC_VDD_30_31 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 						MMC_VDD_32_33   | MMC_VDD_33_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		.name			= "internal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.slots[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		.set_power		= n8x0_mmc_set_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		.set_bus_mode		= n8x0_mmc_set_bus_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		.get_cover_state	= n8x0_mmc_get_cover_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.ocr_mask		= MMC_VDD_165_195 | MMC_VDD_20_21 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 						MMC_VDD_21_22 | MMC_VDD_22_23 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 						MMC_VDD_23_24 | MMC_VDD_24_25 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 						MMC_VDD_27_28 | MMC_VDD_28_29 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 						MMC_VDD_29_30 | MMC_VDD_30_31 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 						MMC_VDD_32_33 | MMC_VDD_33_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.name			= "external",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct gpio n810_emmc_gpios[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	{ N810_EMMC_VSD_GPIO, GPIOF_OUT_INIT_LOW,  "MMC slot 2 Vddf" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	{ N810_EMMC_VIO_GPIO, GPIOF_OUT_INIT_LOW,  "MMC slot 2 Vdd"  },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void __init n8x0_mmc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	if (board_is_n810()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		mmc1_data.slots[0].name = "external";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		 * Some Samsung Movinand chips do not like open-ended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		 * multi-block reads and fall to braind-dead state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		 * while doing so. Reducing the number of blocks in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		 * the transfer or delays in clock disable do not help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		mmc1_data.slots[1].name = "internal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		mmc1_data.slots[1].ban_openended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	err = gpio_request_one(N8X0_SLOT_SWITCH_GPIO, GPIOF_OUT_INIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 			       "MMC slot switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	if (board_is_n810()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		err = gpio_request_array(n810_emmc_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 					 ARRAY_SIZE(n810_emmc_gpios));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 			gpio_free(N8X0_SLOT_SWITCH_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	mmc1_data.nr_slots = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	mmc_data[0] = &mmc1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static struct omap_mmc_platform_data mmc1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void __init n8x0_mmc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #endif	/* CONFIG_MMC_OMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #ifdef CONFIG_MENELAUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int n8x0_auto_sleep_regulators(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	val = EN_VPLL_SLEEP | EN_VMMC_SLEEP    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		| EN_VAUX_SLEEP | EN_VIO_SLEEP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		| EN_VMEM_SLEEP | EN_DC3_SLEEP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		| EN_VC_SLEEP | EN_DC2_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	ret = menelaus_set_regulator_sleep(1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		pr_err("Could not set regulators to sleep on menelaus: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		       ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int n8x0_auto_voltage_scale(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	ret = menelaus_set_vcore_hw(1400, 1050);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int n8x0_menelaus_late_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	ret = n8x0_auto_voltage_scale();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	ret = n8x0_auto_sleep_regulators();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int n8x0_menelaus_late_init(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct menelaus_platform_data n8x0_menelaus_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	.late_init = n8x0_menelaus_late_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct aic3x_pdata n810_aic33_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	.gpio_reset = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int __init n8x0_late_initcall(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	if (!board_caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	n8x0_mmc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	n8x0_usb_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) omap_late_initcall(n8x0_late_initcall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)  * Legacy init pdata init for n8x0. Note that we want to follow the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)  * I2C bus numbering starting at 0 for device tree like other omaps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) void * __init n8x0_legacy_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	board_check_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	spi_register_board_info(n800_spi_board_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 				ARRAY_SIZE(n800_spi_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	return &mmc1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }