^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/arch/arm/mach-omap1/timer32k.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * OMAP 32K Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 - 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Partial timer rewrite and additional dynamic tick timer support by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Tony Lindgen <tony@atomide.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * OMAP Dual-mode timer framework support by Timo Teras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MPU timer code based on the older MPU timer code for OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2000 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Author: Greg Lonnon <glonnon@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <plat/counter-32k.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 32KHz OS timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * This currently works only on 16xx, as 1510 does not have the continuous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * on 1510 would be possible, but the timer would not be as accurate as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * with the 32KHz synchronized timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 16xx specific defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OMAP1_32K_TIMER_BASE 0xfffb9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OMAP1_32KSYNC_TIMER_BASE 0xfffbc400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OMAP1_32K_TIMER_CR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OMAP1_32K_TIMER_TVR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OMAP1_32K_TIMER_TCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OMAP_32K_TICKS_PER_SEC (32768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * so with HZ = 128, TVR = 255.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OMAP_32K_TIMER_TICK_PERIOD ((OMAP_32K_TICKS_PER_SEC / HZ) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (((nr_jiffies) * (clock_rate)) / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void omap_32k_timer_write(int val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline void omap_32k_timer_start(unsigned long load_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!load_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) load_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void omap_32k_timer_stop(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) omap_32k_timer_write(0x0, OMAP1_32K_TIMER_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define omap_32k_timer_ack_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int omap_32k_timer_set_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clock_event_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) omap_32k_timer_start(delta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int omap_32k_timer_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) omap_32k_timer_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int omap_32k_timer_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) omap_32k_timer_stop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct clock_event_device clockevent_32k_timer = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "32k-timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .set_next_event = omap_32k_timer_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .set_state_shutdown = omap_32k_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .set_state_periodic = omap_32k_timer_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .set_state_oneshot = omap_32k_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .tick_resume = omap_32k_timer_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clock_event_device *evt = &clockevent_32k_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) omap_32k_timer_ack_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static __init void omap_init_32k_timer(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (request_irq(INT_OS_TIMER, omap_32k_timer_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clockevent_32k_timer.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clockevents_config_and_register(&clockevent_32k_timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Timer initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int __init omap_32k_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (cpu_is_omap16xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk *sync32k_ick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) base = ioremap(OMAP1_32KSYNC_TIMER_BASE, SZ_1K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_err("32k_counter: failed to map base addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) sync32k_ick = clk_get(NULL, "omap_32ksync_ick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!IS_ERR(sync32k_ick))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) clk_enable(sync32k_ick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = omap_init_clocksource_32k(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) omap_init_32k_timer();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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