^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/arch/arm/mach-omap1/time.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * OMAP Timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Partial timer rewrite and additional dynamic tick timer support by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Tony Lindgen <tony@atomide.com> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * MPU timer code based on the older MPU timer code for OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2000 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Greg Lonnon <glonnon@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/sched_clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef CONFIG_OMAP_MPU_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OMAP_MPU_TIMER_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 cntl; /* CNTL_TIMER, R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 load_tim; /* LOAD_TIM, W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 read_tim; /* READ_TIM, R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) } omap_mpu_timer_regs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define omap_mpu_timer_base(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) (n)*OMAP_MPU_TIMER_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline unsigned long notrace omap_mpu_timer_read(int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return readl(&timer->read_tim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline void omap_mpu_set_autoreset(int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline void omap_mpu_remove_autoreset(int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int autoreset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (autoreset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) timerflags |= MPU_TIMER_AR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel(load_val, &timer->load_tim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(timerflags, &timer->cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void omap_mpu_timer_stop(int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * MPU timer 1 ... count down to zero, interrupt, reload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int omap_mpu_set_next_event(unsigned long cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) omap_mpu_timer_start(0, cycles, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int omap_mpu_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) omap_mpu_timer_stop(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) omap_mpu_remove_autoreset(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int omap_mpu_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) omap_mpu_set_autoreset(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clock_event_device clockevent_mpu_timer1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "mpu_timer1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .set_next_event = omap_mpu_set_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .set_state_periodic = omap_mpu_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .set_state_oneshot = omap_mpu_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct clock_event_device *evt = &clockevent_mpu_timer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static __init void omap_init_mpu_timer(unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (request_irq(INT_TIMER1, omap_mpu_timer1_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IRQF_TIMER | IRQF_IRQPOLL, "mpu_timer1", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_err("Failed to request irq %d (mpu_timer1)\n", INT_TIMER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) clockevent_mpu_timer1.cpumask = cpumask_of(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clockevents_config_and_register(&clockevent_mpu_timer1, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 1, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * MPU timer 2 ... free running 32-bit clock source and scheduler clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static u64 notrace omap_mpu_read_sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ~omap_mpu_timer_read(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void __init omap_init_clocksource(unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static char err[] __initdata = KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "%s: can't register clocksource!\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) omap_mpu_timer_start(1, ~0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sched_clock_register(omap_mpu_read_sched_clock, 32, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 300, 32, clocksource_mmio_readl_down))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) printk(err, "mpu_timer2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void __init omap_mpu_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct clk *ck_ref = clk_get(NULL, "ck_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BUG_ON(IS_ERR(ck_ref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rate = clk_get_rate(ck_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clk_put(ck_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* PTV = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) omap_init_mpu_timer(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) omap_init_clocksource(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static inline void omap_mpu_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pr_err("Bogus timer, should not happen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #endif /* CONFIG_OMAP_MPU_TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Timer initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void __init omap1_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (omap_32k_timer_init() != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) omap_mpu_timer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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