Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * linux/arch/arm/plat-omap/sram-fn.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Functions that need to be run in internal SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * Reprograms ULPD and CKCTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.align	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ENTRY(omap1_sram_reprogram_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	stmfd	sp!, {r0 - r12, lr}		@ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	mov	r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	orr	r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	orr	r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	mov	r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	orr	r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	orr	r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	tst	r0, #1 << 4			@ want lock mode?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	beq	newck				@ nope
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	bic	r0, r0, #1 << 4			@ else clear lock bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	strh	r0, [r2]			@ set dpll into bypass mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	orr	r0, r0, #1 << 4			@ set lock bit again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) newck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	strh	r1, [r3]			@ write new ckctl value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	strh	r0, [r2]			@ write new dpll value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	mov	r4, #0x0700			@ let the clocks settle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	orr	r4, r4, #0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) delay:	sub	r4, r4, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	cmp	r4, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	bne	delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) lock:	ldrh	r4, [r2], #0			@ read back dpll value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	tst	r0, #1 << 4			@ want lock mode?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	beq	out				@ nope
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	tst	r4, #1 << 0			@ dpll rate locked?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	beq	lock				@ try again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	ldmfd	sp!, {r0 - r12, pc}		@ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ENTRY(omap1_sram_reprogram_clock_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	.word	. - omap1_sram_reprogram_clock