Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP SRAM detection and management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2005 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Written by Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/fncpy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/tlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP1_SRAM_PA		0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SRAM_BOOTLOADER_SZ	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * The amount of SRAM depends on the core type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * Note that we cannot try to test for SRAM here because writes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * to secure SRAM will hang the system. Also the SRAM is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * yet mapped at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void __init omap_detect_and_map_sram(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	unsigned long omap_sram_skip = SRAM_BOOTLOADER_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	unsigned long omap_sram_start = OMAP1_SRAM_PA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	unsigned long omap_sram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		omap_sram_size = 0x32000;	/* 200K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	else if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		omap_sram_size = 0x30000;	/* 192K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	else if (cpu_is_omap1610() || cpu_is_omap1611() ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			cpu_is_omap1621() || cpu_is_omap1710())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		omap_sram_size = 0x4000;	/* 16K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		pr_err("Could not detect SRAM size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		omap_sram_size = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	omap_map_sram(omap_sram_start, omap_sram_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		omap_sram_skip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	BUG_ON(!_omap_sram_reprogram_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	/* On 730, bit 13 must always be 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		ckctl |= 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	_omap_sram_reprogram_clock(dpllctl, ckctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int __init omap_sram_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	omap_detect_and_map_sram();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	_omap_sram_reprogram_clock =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 			omap_sram_push(omap1_sram_reprogram_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 					omap1_sram_reprogram_clock_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }