Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * linux/arch/arm/mach-omap1/sleep.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Low-level OMAP7XX/1510/1610 sleep/wakeUp support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Initial SA1110 code:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Adapted for PXA by Nicolas Pitre:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (c) 2002 Monta Vista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Support for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * Forces OMAP into deep sleep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * omapXXXX_cpu_suspend()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * The values of the registers ARM_IDLECT1 and ARM_IDLECT2 are passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * as arg0 and arg1 from caller. arg0 is stored in register r0 and arg1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * in register r1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * Note: This code get's copied to internal SRAM at boot. When the OMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *	 wakes up it continues execution at the point it went to sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Note: Because of errata work arounds we have processor specific functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *       here. They are mostly the same, but slightly different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.align	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) ENTRY(omap7xx_cpu_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	@ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	stmfd	sp!, {r0 - r12, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	@ Drain write cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	mov	r4, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	mcr	p15, 0, r0, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	@ load base address of Traffic Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	mov	r6, #TCMIF_ASM_BASE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	orr	r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	orr	r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	@ prepare to put SDRAM into self-refresh manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ldr	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	orr	r9, r7, #SELF_REFRESH_MODE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	orr	r9, r9, #SELF_REFRESH_MODE & 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	str	r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	@ prepare to put EMIFS to Sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ldr	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	orr	r9, r8, #IDLE_EMIFS_REQUEST & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	str	r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	@ load base address of ARM_IDLECT1 and ARM_IDLECT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	@ turn off clock domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	@ do not disable PERCK (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	mov	r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	orr	r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	@ request ARM idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mov	r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	orr	r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	@ disable instruction cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mrc	p15, 0, r9, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	bic	r2, r9, #0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	mcr	p15, 0, r2, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * Let's wait for the next wake up event to wake us up. r0 can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * used here because r0 holds ARM_IDLECT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mov	r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	mcr	p15, 0, r2, c7, c0, 4		@ wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * omap7xx_cpu_suspend()'s resume point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * It will just start executing here, so we'll restore stuff from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	@ re-enable Icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	mcr	p15, 0, r9, c1, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	@ reset the ARM_IDLECT1 and ARM_IDLECT2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	@ Restore EMIFF controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	str	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	str	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	@ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ldmfd	sp!, {r0 - r12, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ENTRY(omap7xx_cpu_suspend_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.word	. - omap7xx_cpu_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_ARCH_OMAP15XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.align	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ENTRY(omap1510_cpu_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	@ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	stmfd	sp!, {r0 - r12, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	@ load base address of Traffic Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mov	r4, #TCMIF_ASM_BASE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	orr	r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	orr	r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	@ work around errata of OMAP1510 PDE bit for TC shut down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	@ clear PDE bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ldr	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	bic	r5, r5, #PDE_BIT & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	@ set PWD_EN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	and	r5, r5, #PWD_EN_BIT & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	@ prepare to put SDRAM into self-refresh manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ldr	r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	orr	r5, r5, #SELF_REFRESH_MODE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	orr	r5, r5, #SELF_REFRESH_MODE & 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	str	r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	@ prepare to put EMIFS to Sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ldr	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	orr	r5, r5, #IDLE_EMIFS_REQUEST & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	str	r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	@ load base address of ARM_IDLECT1 and ARM_IDLECT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	@ turn off clock domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	mov	r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	orr	r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	@ request ARM idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mov	r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	orr	r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	mov	r5, #IDLE_WAIT_CYCLES & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	orr	r5, r5, #IDLE_WAIT_CYCLES & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) l_1510_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	subs	r5, r5, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	bne	l_1510_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * Let's wait for the next wake up event to wake us up. r0 can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * used here because r0 holds ARM_IDLECT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mov	r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mcr	p15, 0, r2, c7, c0, 4		@ wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * omap1510_cpu_suspend()'s resume point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * It will just start executing here, so we'll restore stuff from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	@ restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ldmfd	sp!, {r0 - r12, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ENTRY(omap1510_cpu_suspend_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.word	. - omap1510_cpu_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif /* CONFIG_ARCH_OMAP15XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #if defined(CONFIG_ARCH_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.align	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ENTRY(omap1610_cpu_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	@ save registers on stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	stmfd	sp!, {r0 - r12, lr}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	@ Drain write cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mov	r4, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	mcr	p15, 0, r0, c7, c10, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	@ Load base address of Traffic Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	mov	r6, #TCMIF_ASM_BASE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	orr	r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	orr	r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	@ Prepare to put SDRAM into self-refresh manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ldr	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	orr	r9, r7, #SELF_REFRESH_MODE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	orr	r9, r9, #SELF_REFRESH_MODE & 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	str	r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	@ Prepare to put EMIFS to Sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ldr	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	orr	r9, r8, #IDLE_EMIFS_REQUEST & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	str	r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	@ Load base address of ARM_IDLECT1 and ARM_IDLECT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	mov	r4, #CLKGEN_REG_ASM_BASE & 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	orr	r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	@ Turn off clock domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	@ Do not disable PERCK (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	mov	r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	orr	r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	strh	r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	@ Request ARM idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	mov	r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	orr	r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	strh	r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * Let's wait for the next wake up event to wake us up. r0 can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * used here because r0 holds ARM_IDLECT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mov	r2, #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	mcr	p15, 0, r2, c7, c0, 4		@ wait for interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	@ Errata (HEL3SU467, section 1.4.4) specifies nop-instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	@ according to this formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	@ 2 + (4*DPLL_MULT)/DPLL_DIV/ARMDIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	@ Max DPLL_MULT = 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	@ DPLL_DIV = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	@ ARMDIV = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	@ => 74 nop-instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	nop	@10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	nop	@20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	nop	@30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	nop	@40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	nop	@50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	nop	@60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	nop	@70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	nop	@74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)  * omap1610_cpu_suspend()'s resume point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * It will just start executing here, so we'll restore stuff from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  * stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	@ Restore the ARM_IDLECT1 and ARM_IDLECT2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	strh	r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	strh	r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	@ Restore EMIFF controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	str	r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	str	r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	@ Restore regs and return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	ldmfd	sp!, {r0 - r12, pc}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ENTRY(omap1610_cpu_suspend_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.word	. - omap1610_cpu_suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif /* CONFIG_ARCH_OMAP16XX */