Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-omap1/serial.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * OMAP1 serial support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/serial.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/tty.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/serial_reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static struct clk * uart1_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct clk * uart2_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static struct clk * uart3_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 					  int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	offset <<= up->regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	return (unsigned int)__raw_readb(up->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 				    int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	offset <<= p->regshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	__raw_writeb(value, p->membase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * Internal UARTs need to be initialized for the 8250 autoconfig to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * properly. Note that the TX watermark initialization may not be needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * once the 8250.c watermark handling code is merged.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void __init omap_serial_reset(struct plat_serial8250_port *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	omap_serial_outp(p, UART_OMAP_MDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			UART_OMAP_MDR1_DISABLE);	/* disable UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	omap_serial_outp(p, UART_OMAP_SCR, 0x08);	/* TX watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	omap_serial_outp(p, UART_OMAP_MDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			UART_OMAP_MDR1_16X_MODE);	/* enable UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (!cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct plat_serial8250_port serial_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.mapbase	= OMAP1_UART1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.irq		= INT_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.flags		= UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.uartclk	= OMAP16XX_BASE_BAUD * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.mapbase	= OMAP1_UART2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.irq		= INT_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.flags		= UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.uartclk	= OMAP16XX_BASE_BAUD * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.mapbase	= OMAP1_UART3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.irq		= INT_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.flags		= UPF_BOOT_AUTOCONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.iotype		= UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.regshift	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.uartclk	= OMAP16XX_BASE_BAUD * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static struct platform_device serial_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.name			= "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.id			= PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.dev			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.platform_data	= serial_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * Note that on Innovator-1510 UART2 pins conflict with USB2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * By default UART2 does not work on Innovator-1510 if you have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * USB OHCI enabled. To use UART2, you must disable USB2 first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __init omap_serial_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (cpu_is_omap7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		serial_platform_data[0].regshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		serial_platform_data[1].regshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/* Don't look at UARTs higher than 2 for omap7xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (cpu_is_omap7xx() && i > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			serial_platform_data[i].membase = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			serial_platform_data[i].mapbase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		/* Static mapping, never released */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		serial_platform_data[i].membase =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			ioremap(serial_platform_data[i].mapbase, SZ_2K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if (!serial_platform_data[i].membase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			printk(KERN_ERR "Could not ioremap uart%i\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			uart1_ck = clk_get(NULL, "uart1_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			if (IS_ERR(uart1_ck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				printk("Could not get uart1_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				clk_enable(uart1_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 				if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					clk_set_rate(uart1_ck, 12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			uart2_ck = clk_get(NULL, "uart2_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			if (IS_ERR(uart2_ck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 				printk("Could not get uart2_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				clk_enable(uart2_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					clk_set_rate(uart2_ck, 12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 					clk_set_rate(uart2_ck, 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			uart3_ck = clk_get(NULL, "uart3_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			if (IS_ERR(uart3_ck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				printk("Could not get uart3_ck\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				clk_enable(uart3_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 					clk_set_rate(uart3_ck, 12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		omap_serial_reset(&serial_platform_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #ifdef CONFIG_OMAP_SERIAL_WAKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Need to do something with serial port right after wake-up? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * Reroutes serial RX lines to GPIO lines for the duration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * sleep to allow waking up the device from serial port even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * in deep sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void omap_serial_wake_trigger(int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (!cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if (uart1_ck != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			omap_cfg_reg(V14_16XX_GPIO37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			omap_cfg_reg(V14_16XX_UART1_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (uart2_ck != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			omap_cfg_reg(R9_16XX_GPIO18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			omap_cfg_reg(R9_16XX_UART2_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (uart3_ck != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			omap_cfg_reg(L14_16XX_GPIO49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			omap_cfg_reg(L14_16XX_UART3_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void __init omap_serial_set_port_wakeup(int gpio_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	ret = gpio_request(gpio_nr, "UART wake");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		       gpio_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	gpio_direction_input(gpio_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			  IRQF_TRIGGER_RISING, "serial wakeup", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		gpio_free(gpio_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		       gpio_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	enable_irq_wake(gpio_to_irq(gpio_nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int __init omap_serial_wakeup_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (uart1_ck != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		omap_serial_set_port_wakeup(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (uart2_ck != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		omap_serial_set_port_wakeup(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (uart3_ck != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		omap_serial_set_port_wakeup(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif	/* CONFIG_OMAP_SERIAL_WAKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int __init omap_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!cpu_class_is_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return platform_device_register(&serial_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) arch_initcall(omap_init);