Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * OMAP1 reset support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* ARM_SYSST bit shifts related to SoC reset sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARM_SYSST_POR_SHIFT				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ARM_SYSST_EXT_RST_SHIFT				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ARM_SYSST_ARM_WDRST_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ARM_SYSST_GLOB_SWRST_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Standardized reset source bits (across all OMAP SoCs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OMAP_MPU_WD_RST_SRC_ID_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OMAP_EXTWARM_RST_SRC_ID_SHIFT			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void omap1_restart(enum reboot_mode mode, const char *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	 * "Global Software Reset Affects Traffic Controller Frequency".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (cpu_is_omap5912()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		omap_writew(0x8, ARM_RSTCT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	omap_writew(1, ARM_RSTCT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * omap1_get_reset_sources - return the source of the SoC's last reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * Returns bits that represent the last reset source for the SoC.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * format is standardized across OMAPs for use by the OMAP watchdog.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 omap1_get_reset_sources(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u32 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u16 rs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	if (rs & (1 << ARM_SYSST_POR_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		ret |= 1 << OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (rs & (1 << ARM_SYSST_EXT_RST_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		ret |= 1 << OMAP_EXTWARM_RST_SRC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	if (rs & (1 << ARM_SYSST_ARM_WDRST_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		ret |= 1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (rs & (1 << ARM_SYSST_GLOB_SWRST_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		ret |= 1 << OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }