^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-omap1/pm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Header file for OMAP1 Power Management Routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * support@mvista.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2002 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef __ARCH_ARM_MACH_OMAP1_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define __ARCH_ARM_MACH_OMAP1_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Register and offset definitions to be used in PM assembler code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ARM_IDLECT1_ASM_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ARM_IDLECT2_ASM_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EMIFS_CONFIG_ASM_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Power management bitmasks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IDLE_WAIT_CYCLES 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PERIPHERAL_ENABLE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SELF_REFRESH_MODE 0x0c000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IDLE_EMIFS_REQUEST 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MODEM_32K_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PER_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CPU_SUSPEND_SIZE 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ULPD_LOW_PWR_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ULPD_SETUP_ANALOG_CELL_3_VAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ULPD_POWER_CTRL_REG_VAL 0x0219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DSP_IDLE_DELAY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DSP_IDLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DSP_RST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DSP_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SUFFICIENT_DSP_RESET_TIME 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DEFAULT_MPUI_CONFIG 0x05cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ENABLE_XORCLK 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DSP_CLOCK_ENABLE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DSP_IDLE_MODE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TC_IDLE_REQUEST (0x0000000c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IRQ_LEVEL2 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IRQ_KEYBOARD (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IRQ_UART2 (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PDE_BIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PWD_EN_BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EN_PERCK_BIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Both big sleep and deep sleep use same values. Difference is in ULPD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OMAP1610_IDLECT3_VAL 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP1610_IDLECT3 0xfffece24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP1610_IDLE_LOOP_REQUEST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OMAP7XX_IDLECT3_VAL 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OMAP7XX_IDLECT3 0xfffece24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if !defined(CONFIG_ARCH_OMAP730) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) !defined(CONFIG_ARCH_OMAP850) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) !defined(CONFIG_ARCH_OMAP15XX) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) !defined(CONFIG_ARCH_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #warning "Power management for this processor not implemented yet"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifndef __ASSEMBLER__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern struct kset power_subsys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern void prevent_idle_sleep(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern void allow_idle_sleep(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern void omap1_pm_idle(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern void omap1_pm_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern void omap7xx_cpu_suspend(unsigned long, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern void omap1510_cpu_suspend(unsigned long, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern void omap1610_cpu_suspend(unsigned long, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern void omap7xx_idle_loop_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) extern void omap1510_idle_loop_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern void omap1610_idle_loop_suspend(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern unsigned int omap7xx_cpu_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern unsigned int omap1510_cpu_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern unsigned int omap1610_cpu_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern unsigned int omap7xx_idle_loop_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern unsigned int omap1510_idle_loop_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern unsigned int omap1610_idle_loop_suspend_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_OMAP_SERIAL_WAKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern void omap_serial_wake_trigger(int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define omap_serial_wakeup_init() {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define omap_serial_wake_trigger(x) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif /* CONFIG_OMAP_SERIAL_WAKE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * List of global OMAP registers to preserve.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * More ones like CP and general purpose register values are preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * with the stack pointer in sleep.S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) enum arm_save_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ARM_SLEEP_SAVE_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * MPU control registers 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ARM_SLEEP_SAVE_ARM_CKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ARM_SLEEP_SAVE_ARM_IDLECT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ARM_SLEEP_SAVE_ARM_IDLECT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ARM_SLEEP_SAVE_ARM_IDLECT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ARM_SLEEP_SAVE_ARM_EWUPCT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ARM_SLEEP_SAVE_ARM_RSTCT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ARM_SLEEP_SAVE_ARM_RSTCT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ARM_SLEEP_SAVE_ARM_SYSST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ARM_SLEEP_SAVE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum dsp_save_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DSP_SLEEP_SAVE_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * DSP registers 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DSP_SLEEP_SAVE_DSP_IDLECT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DSP_SLEEP_SAVE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum ulpd_save_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ULPD_SLEEP_SAVE_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * ULPD registers 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ULPD_SLEEP_SAVE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enum mpui1510_save_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MPUI1510_SLEEP_SAVE_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * MPUI registers 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MPUI1510_SLEEP_SAVE_MPUI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #if defined(CONFIG_ARCH_OMAP15XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MPUI1510_SLEEP_SAVE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MPUI1510_SLEEP_SAVE_SIZE = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum mpui7xx_save_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MPUI7XX_SLEEP_SAVE_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * MPUI registers 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MPUI7XX_SLEEP_SAVE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MPUI7XX_SLEEP_SAVE_SIZE = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) enum mpui1610_save_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MPUI1610_SLEEP_SAVE_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * MPUI registers 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MPUI1610_SLEEP_SAVE_MPUI_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #if defined(CONFIG_ARCH_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MPUI1610_SLEEP_SAVE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MPUI1610_SLEEP_SAVE_SIZE = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif /* ASSEMBLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif /* __ASM_ARCH_OMAP_PM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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