^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap1/mux.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * OMAP1 pin multiplexing configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2003 - 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Written by Tony Lindgren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_OMAP_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct omap_mux_cfg arch_mux_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static struct pin_config omap7xx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* MMC Pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* SPI pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MUX_CFG_7XX("SPI_7XX_1", 6, 5, 4, 4, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MUX_CFG_7XX("SPI_7XX_2", 6, 9, 4, 8, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* UART pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define omap7xx_pins NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OMAP7XX_PINS_SZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct pin_config omap1xxx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * description mux mode mux pull pull pull pu_pd pu dbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * reg offset mode reg bit ena reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* UART2 (COM_UART_GATING), conflicts with USB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* UART3 (GIGA_UART_GATING) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* PWT & PWL, conflicts with UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* USB internal master generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* USB1 master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* USB2 master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* OMAP-1510 GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* OMAP1610 GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* OMAP-1710 GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* MPUIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* MCBSP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* MCBSP3 NOTE: Mode must 1 for clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Misc ballouts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* OMAP-1610 MMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* OMAP-1610 External Trace Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* OMAP16XX GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* OMAP-1610 uWire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* OMAP-1610 SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* OMAP-1610 Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* First MMC interface, same on 1510, 1610 and 1710 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* OMAP-1610 USB0 alternate configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* USB2 interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 16XX UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* I2C interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Keypad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* MCLK Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* CompactFlash controller, conflicts with MMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* parallel camera */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* serial camera */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define omap1xxx_pins NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define OMAP1XXX_PINS_SZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int omap1_cfg_reg(const struct pin_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static DEFINE_SPINLOCK(mux_spin_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pull_orig = 0, pull = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned int mask, warn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Check the mux register in question */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (cfg->mux_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned tmp1, tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_lock_irqsave(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg_orig = omap_readl(cfg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* The mux registers always seem to be 3 bits long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mask = (0x7 << cfg->mask_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tmp1 = reg_orig & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reg = reg_orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tmp2 = (cfg->mask << cfg->mask_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) reg |= tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (tmp1 != tmp2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) warn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) omap_writel(reg, cfg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spin_unlock_irqrestore(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Check for pull up or pull down selection on 1610 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (cfg->pu_pd_reg && cfg->pull_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) spin_lock_irqsave(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pu_pd_orig = omap_readl(cfg->pu_pd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mask = 1 << cfg->pull_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (cfg->pu_pd_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!(pu_pd_orig & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) warn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Use pull up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pu_pd = pu_pd_orig | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (pu_pd_orig & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) warn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Use pull down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pu_pd = pu_pd_orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) omap_writel(pu_pd, cfg->pu_pd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spin_unlock_irqrestore(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Check for an associated pull down register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (cfg->pull_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spin_lock_irqsave(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pull_orig = omap_readl(cfg->pull_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mask = 1 << cfg->pull_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (cfg->pull_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (pull_orig & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) warn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Low bit = pull enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pull = pull_orig & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!(pull_orig & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) warn = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* High bit = pull disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pull = pull_orig | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) omap_writel(pull, cfg->pull_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spin_unlock_irqrestore(&mux_spin_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (warn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef CONFIG_OMAP_MUX_WARNINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #ifdef CONFIG_OMAP_MUX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (cfg->debug || warn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) printk("MUX: Setting register %s\n", cfg->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (cfg->pu_pd_reg && cfg->pull_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cfg->pu_pd_name, cfg->pu_pd_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) pu_pd_orig, pu_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (cfg->pull_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cfg->pull_name, cfg->pull_reg, pull_orig, pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #ifdef CONFIG_OMAP_MUX_WARNINGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return warn ? -ETXTBSY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static struct omap_mux_cfg *mux_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) || !arch_mux_cfg->cfg_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) printk(KERN_ERR "Invalid pin table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) mux_cfg = arch_mux_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Sets the Omap MUX and PULL_DWN registers based on the table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int omap_cfg_reg(const unsigned long index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct pin_config *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!cpu_class_is_omap1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (mux_cfg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) printk(KERN_ERR "Pin mux table not initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (index >= mux_cfg->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) index, mux_cfg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dump_stack();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) reg = &mux_cfg->pins[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!mux_cfg->cfg_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return mux_cfg->cfg_reg(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) EXPORT_SYMBOL(omap_cfg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int __init omap1_mux_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (cpu_is_omap7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) arch_mux_cfg.pins = omap7xx_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) arch_mux_cfg.size = OMAP7XX_PINS_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) arch_mux_cfg.cfg_reg = omap1_cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) arch_mux_cfg.pins = omap1xxx_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) arch_mux_cfg.cfg_reg = omap1_cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return omap_mux_register(&arch_mux_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define omap_mux_init() do {} while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define omap_cfg_reg(x) do {} while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #endif /* CONFIG_OMAP_MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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