^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap1/mcbsp.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Instituto Nokia de Tecnologia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Multichannel mode not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_data/asoc-ti-mcbsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DPS_RSTCT2_PER_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DSP_RSTCT2_WD_PER_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int dsp_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct clk *api_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct clk *dsp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct platform_device **omap_mcbsp_devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void omap1_mcbsp_request(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * On 1510, 1610 and 1710, McBSP1 and McBSP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * are DSP public peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (id == 0 || id == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (dsp_use++ == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) api_clk = clk_get(NULL, "api_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dsp_clk = clk_get(NULL, "dsp_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) clk_enable(api_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clk_enable(dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * DSP external peripheral reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * FIXME: This should be moved to dsp code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void omap1_mcbsp_free(unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (id == 0 || id == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (--dsp_use == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!IS_ERR(api_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clk_disable(api_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk_put(api_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!IS_ERR(dsp_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_disable(dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clk_put(dsp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static struct omap_mcbsp_ops omap1_mcbsp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .request = omap1_mcbsp_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .free = omap1_mcbsp_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP7XX_MCBSP1_BASE 0xfffb1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP7XX_MCBSP2_BASE 0xfffb1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP1510_MCBSP1_BASE 0xe1011800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP1510_MCBSP2_BASE 0xfffb1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP1510_MCBSP3_BASE 0xe1017000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP1610_MCBSP1_BASE 0xe1011800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OMAP1610_MCBSP2_BASE 0xfffb1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OMAP1610_MCBSP3_BASE 0xe1017000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct resource omap7xx_mcbsp_res[][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .start = OMAP7XX_MCBSP1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .end = OMAP7XX_MCBSP1_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .start = INT_7XX_McBSP1RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .start = INT_7XX_McBSP1TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .start = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .start = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .start = OMAP7XX_MCBSP2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .end = OMAP7XX_MCBSP2_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .start = INT_7XX_McBSP2RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .start = INT_7XX_McBSP2TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .start = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .start = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define omap7xx_mcbsp_res_0 NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define omap7xx_mcbsp_pdata NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define OMAP7XX_MCBSP_RES_SZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OMAP7XX_MCBSP_COUNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef CONFIG_ARCH_OMAP15XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct resource omap15xx_mcbsp_res[][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .start = OMAP1510_MCBSP1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .end = OMAP1510_MCBSP1_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .start = INT_McBSP1RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .start = INT_McBSP1TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .start = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .start = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .start = OMAP1510_MCBSP2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .end = OMAP1510_MCBSP2_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .start = INT_1510_SPI_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .start = INT_1510_SPI_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .start = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .start = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .start = OMAP1510_MCBSP3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .end = OMAP1510_MCBSP3_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .start = INT_McBSP3RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .start = INT_McBSP3TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .start = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .start = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define omap15xx_mcbsp_res_0 NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define omap15xx_mcbsp_pdata NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP15XX_MCBSP_RES_SZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OMAP15XX_MCBSP_COUNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef CONFIG_ARCH_OMAP16XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct resource omap16xx_mcbsp_res[][6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .start = OMAP1610_MCBSP1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .end = OMAP1610_MCBSP1_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .start = INT_McBSP1RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .start = INT_McBSP1TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .start = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .start = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .start = OMAP1610_MCBSP2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .end = OMAP1610_MCBSP2_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .start = INT_1610_McBSP2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .start = INT_1610_McBSP2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .start = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .start = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .start = OMAP1610_MCBSP3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .end = OMAP1610_MCBSP3_BASE + SZ_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .start = INT_McBSP3RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .start = INT_McBSP3TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .start = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .start = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .ops = &omap1_mcbsp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define omap16xx_mcbsp_res_0 NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define omap16xx_mcbsp_pdata NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define OMAP16XX_MCBSP_RES_SZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OMAP16XX_MCBSP_COUNT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct omap_mcbsp_platform_data *config, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) omap_mcbsp_devices = kcalloc(size, sizeof(struct platform_device *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!omap_mcbsp_devices) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) printk(KERN_ERR "Could not register McBSP devices\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct platform_device *new_mcbsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!new_mcbsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) platform_device_add_resources(new_mcbsp, &res[i * res_count],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) res_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) config[i].reg_size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) config[i].reg_step = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) new_mcbsp->dev.platform_data = &config[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = platform_device_add(new_mcbsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) platform_device_put(new_mcbsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) omap_mcbsp_devices[i] = new_mcbsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int __init omap1_mcbsp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!cpu_class_is_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) OMAP7XX_MCBSP_RES_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) omap7xx_mcbsp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) OMAP7XX_MCBSP_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) OMAP15XX_MCBSP_RES_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) omap15xx_mcbsp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) OMAP15XX_MCBSP_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) OMAP16XX_MCBSP_RES_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) omap16xx_mcbsp_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) OMAP16XX_MCBSP_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) arch_initcall(omap1_mcbsp_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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