^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * linux/arch/arm/mach-omap1/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Interrupt handler for all OMAP boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Written by Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Completely re-written to support various OMAP chips with bank specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * interrupt handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Some snippets of the code taken from the older OMAP interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * GPIO interrupt handler moved to gpio.c by Juha Yrjola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/exception.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IRQ_BANK(irq) ((irq) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IRQ_BIT(irq) ((irq) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct omap_irq_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long base_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long trigger_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned long wake_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static u32 omap_l2_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static unsigned int irq_bank_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct omap_irq_bank *irq_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline unsigned int irq_bank_readl(int bank, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return readl_relaxed(irq_banks[bank].va + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline void irq_bank_writel(unsigned long value, int bank, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel_relaxed(value, irq_banks[bank].va + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void omap_ack_irq(int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (irq > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void omap_mask_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct irq_chip_type *ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ct->chip.irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) omap_ack_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Allows tuning the IRQ type and priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * NOTE: There is currently no OMAP fiq handler for Linux. Read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * mailing list threads on FIQ handlers if you are planning to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * add a FIQ handler for OMAP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) signed int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long val, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bank = IRQ_BANK(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* FIQ is only available on bank 0 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) fiq = bank ? 0 : (fiq & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) irq_bank_writel(val, bank, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct omap_irq_bank omap7xx_irq_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_ARCH_OMAP15XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct omap_irq_bank omap1510_irq_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct omap_irq_bank omap310_irq_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #if defined(CONFIG_ARCH_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct omap_irq_bank omap1610_irq_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *l1 = irq_banks[0].va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __iomem *l2 = irq_banks[1].va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 irqnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (irqnr == omap_l2_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) irqnr += 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) handle_domain_irq(domain, irqnr, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } while (irqnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static __init void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct irq_chip_generic *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) gc = irq_alloc_generic_chip("MPU", 1, irq_start, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ct = gc->chip_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ct->chip.irq_ack = omap_mask_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ct->chip.irq_mask = irq_gc_mask_set_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ct->chip.irq_unmask = irq_gc_mask_clr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ct->chip.irq_set_wake = irq_gc_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ct->regs.mask = IRQ_MIR_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IRQ_NOREQUEST | IRQ_NOPROBE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void __init omap1_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct irq_chip_type *ct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct irq_data *d = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int i, j, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned long nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (cpu_is_omap7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) irq_banks = omap7xx_irq_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_ARCH_OMAP15XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (cpu_is_omap1510()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) irq_banks = omap1510_irq_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (cpu_is_omap310()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) irq_banks = omap310_irq_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if defined(CONFIG_ARCH_OMAP16XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (cpu_is_omap16xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) irq_banks = omap1610_irq_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < irq_bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (WARN_ON(!irq_banks[i].va))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) nr_irqs = irq_bank_count * 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pr_warn("Couldn't allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) irq_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) omap_l2_irq -= NR_IRQS_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) &irq_domain_simple_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pr_info("Total of %lu interrupts in %i interrupt banks\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) nr_irqs, irq_bank_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Mask and clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (i = 0; i < irq_bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Enable interrupts in global mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Install the interrupt handlers for each bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) for (i = 0; i < irq_bank_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (j = i * 32; j < (i + 1) * 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int irq_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) omap_irq_set_cfg(j, 0, 0, irq_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) irq_clear_status_flags(j, IRQ_NOREQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Unmask level 2 handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ct = irq_data_get_chip_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ct->chip.irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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