Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Interrupt handler for OMAP-1510 FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2001 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Greg Lonnon <glonnon@ridgerun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2002 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef __ASM_ARCH_OMAP_FPGA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define __ASM_ARCH_OMAP_FPGA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *  H2/P2 Debug board FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* maps in the FPGA registers and the ETHR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define H2P2_DBG_FPGA_BASE		0xE8000000		/* VA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define H2P2_DBG_FPGA_SIZE		SZ_4K			/* SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define H2P2_DBG_FPGA_START		0x04000000		/* PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define H2P2_DBG_FPGA_ETHR_START	(H2P2_DBG_FPGA_START + 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define H2P2_DBG_FPGA_FPGA_REV		IOMEM(H2P2_DBG_FPGA_BASE + 0x10)	/* FPGA Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define H2P2_DBG_FPGA_BOARD_REV		IOMEM(H2P2_DBG_FPGA_BASE + 0x12)	/* Board Revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define H2P2_DBG_FPGA_GPIO		IOMEM(H2P2_DBG_FPGA_BASE + 0x14)	/* GPIO outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define H2P2_DBG_FPGA_LEDS		IOMEM(H2P2_DBG_FPGA_BASE + 0x16)	/* LEDs outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define H2P2_DBG_FPGA_MISC_INPUTS	IOMEM(H2P2_DBG_FPGA_BASE + 0x18)	/* Misc inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define H2P2_DBG_FPGA_LAN_STATUS	IOMEM(H2P2_DBG_FPGA_BASE + 0x1A)	/* LAN Status line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define H2P2_DBG_FPGA_LAN_RESET		IOMEM(H2P2_DBG_FPGA_BASE + 0x1C)	/* LAN Reset line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* LEDs definition on debug board (16 LEDs, all physically green) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define H2P2_DBG_FPGA_LED_GREEN		(1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define H2P2_DBG_FPGA_LED_AMBER		(1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define H2P2_DBG_FPGA_LED_RED		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define H2P2_DBG_FPGA_LED_BLUE		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*  cpu0 load-meter LEDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define H2P2_DBG_FPGA_LOAD_METER	(1 << 0)	// A bit of fun on our board ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define H2P2_DBG_FPGA_LOAD_METER_SIZE	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define H2P2_DBG_FPGA_LOAD_METER_MASK	((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define H2P2_DBG_FPGA_P2_LED_TIMER		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define H2P2_DBG_FPGA_P2_LED_IDLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif