^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP1/OMAP7xx - specific DMA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 - 2008 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Juha Yrjölä <juha.yrjola@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Graphics DMA and LCD DMA graphics tranformations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * by Imre Deak <imre.deak@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Converted DMA library into platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - G, Manjunath Kondaiah <manjugk@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/omap-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/tc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OMAP1_DMA_BASE (0xfffed800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static u32 enable_1510_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct omap_dma_reg reg_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [GSCR] = { 0x0404, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [GRST1] = { 0x0408, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [HW_ID] = { 0x0442, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [PCH2_ID] = { 0x0444, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [PCH0_ID] = { 0x0446, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [PCH1_ID] = { 0x0448, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [PCHG_ID] = { 0x044a, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [PCHD_ID] = { 0x044c, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [CAPS_0] = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [CAPS_1] = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [CAPS_2] = { 0x0456, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [CAPS_3] = { 0x0458, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) [CAPS_4] = { 0x045a, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [PCH2_SR] = { 0x0460, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [PCH0_SR] = { 0x0480, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) [PCH1_SR] = { 0x0482, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [PCHD_SR] = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Common Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [CSDP] = { 0x0000, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [CICR] = { 0x0004, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) [CEN] = { 0x0010, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [CFN] = { 0x0012, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) [CSFI] = { 0x0014, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [CSEI] = { 0x0016, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [CPC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [CSAC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [CDAC] = { 0x001a, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [CDEI] = { 0x001c, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [CDFI] = { 0x001e, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [CLNK_CTRL] = { 0x0028, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Channel specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [CSSA] = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [CDSA] = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [COLOR] = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [LCH_CTRL] = { 0x002a, 0x40, OMAP_DMA_REG_16BIT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct resource res[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .start = OMAP1_DMA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .end = OMAP1_DMA_BASE + SZ_2K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .start = INT_DMA_CH0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .start = INT_DMA_CH1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .start = INT_DMA_CH2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .start = INT_DMA_CH3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .start = INT_DMA_CH4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .name = "5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .start = INT_DMA_CH5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Handled in lcd_dma.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .start = INT_1610_DMA_CH6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* irq's for omap16xx and omap7xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .start = INT_1610_DMA_CH7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .start = INT_1610_DMA_CH8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .start = INT_1610_DMA_CH9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .start = INT_1610_DMA_CH10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .start = INT_1610_DMA_CH11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .start = INT_1610_DMA_CH12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .start = INT_1610_DMA_CH13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [15] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .start = INT_1610_DMA_CH14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .name = "15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .start = INT_1610_DMA_CH15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [17] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .start = INT_DMA_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __iomem *dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline void dma_write(u32 val, int reg, int lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __iomem *addr = dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) addr += reg_map[reg].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) addr += reg_map[reg].stride * lch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __raw_writew(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __raw_writew(val >> 16, addr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline u32 dma_read(int reg, int lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void __iomem *addr = dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) addr += reg_map[reg].offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) addr += reg_map[reg].stride * lch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val = __raw_readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) val |= __raw_readw(addr + 2) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void omap1_clear_lch_regs(int lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = CPC; i <= COLOR; i += 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dma_write(0, i, lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void omap1_clear_dma(int lch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) l = dma_read(CCR, lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) l &= ~OMAP_DMA_CCR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dma_write(l, CCR, lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) l = dma_read(CSR, lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void omap1_show_dma_caps(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (enable_1510_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u16 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) printk(KERN_INFO "OMAP DMA hardware version %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dma_read(HW_ID, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dma_read(CAPS_4, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Disable OMAP 3.0/3.1 compatibility mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) w = dma_read(GSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) w |= 1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dma_write(w, GSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static unsigned configure_dma_errata(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned errata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * read before the DMA controller finished disabling the channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SET_DMA_ERRATA(DMA_ERRATA_3_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct platform_device_info omap_dma_dev_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "omap-dma-engine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .res = res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .num_res = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* OMAP730, OMAP850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct dma_slave_map omap7xx_sdma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* OMAP1510, OMAP1610*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct dma_slave_map omap1xxx_sdma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { "mmci-omap.1", "tx", SDMA_FILTER_PARAM(54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { "mmci-omap.1", "rx", SDMA_FILTER_PARAM(55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct omap_system_dma_plat_info dma_plat_info __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .reg_map = reg_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .channel_stride = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .show_dma_caps = omap1_show_dma_caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .clear_lch_regs = omap1_clear_lch_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .clear_dma = omap1_clear_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .dma_write = dma_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .dma_read = dma_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int __init omap1_system_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct omap_system_dma_plat_info p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct omap_dma_dev_attr *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct platform_device *pdev, *dma_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pdev = platform_device_alloc("omap_dma_system", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pr_err("%s: Unable to device alloc for dma\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dma_base = ioremap(res[0].start, resource_size(&res[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!dma_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pr_err("%s: Unable to ioremap\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) goto exit_device_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __func__, pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) goto exit_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) d = kzalloc(sizeof(*d), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto exit_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Valid attributes for omap1 plus processors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) d->dev_caps = ENABLE_1510_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) d->dev_caps = ENABLE_16XX_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) d->dev_caps |= SRC_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) d->dev_caps |= DST_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) d->dev_caps |= SRC_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) d->dev_caps |= DST_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) d->dev_caps |= IS_BURST_ONLY4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) d->dev_caps |= CLEAR_CSR_ON_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) d->dev_caps |= IS_WORD_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* available logical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (cpu_is_omap15xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) d->lch_count = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (d->dev_caps & ENABLE_1510_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) d->lch_count = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) d->lch_count = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) p = dma_plat_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) p.dma_attr = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) p.errata = configure_dma_errata();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (cpu_is_omap7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) p.slave_map = omap7xx_sdma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) p.slave_map = omap1xxx_sdma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = platform_device_add_data(pdev, &p, sizeof(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) __func__, pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto exit_release_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __func__, pdev->name, pdev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) goto exit_release_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dma_pdev = platform_device_register_full(&omap_dma_dev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (IS_ERR(dma_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ret = PTR_ERR(dma_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) goto exit_release_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) exit_release_pdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) platform_device_del(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) exit_release_d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) kfree(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) exit_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) iounmap(dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) exit_device_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) arch_initcall(omap1_system_dma_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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