^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap1/devices.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * OMAP1 platform device setup/initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_data/omap-wd-timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <mach/tc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <mach/omap7xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "mmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #if IS_ENABLED(CONFIG_RTC_DRV_OMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OMAP_RTC_BASE 0xfffb4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct resource rtc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .start = OMAP_RTC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .end = OMAP_RTC_BASE + 0x5f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .start = INT_RTC_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .start = INT_RTC_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct platform_device omap_rtc_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = "omap_rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .num_resources = ARRAY_SIZE(rtc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .resource = rtc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void omap_init_rtc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (void) platform_device_register(&omap_rtc_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void omap_init_rtc(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void omap_init_mbox(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #if IS_ENABLED(CONFIG_MMC_OMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int controller_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (controller_nr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (cpu_is_omap7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) omap_cfg_reg(MMC_7XX_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) omap_cfg_reg(MMC_7XX_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) omap_cfg_reg(MMC_7XX_DAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) omap_cfg_reg(MMC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) omap_cfg_reg(MMC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) omap_cfg_reg(MMC_DAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (cpu_is_omap1710()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) omap_cfg_reg(M15_1710_MMC_CLKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) omap_cfg_reg(P19_1710_MMC_CMDDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) omap_cfg_reg(P20_1710_MMC_DATDIR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) omap_cfg_reg(MMC_DAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* NOTE: DAT2 can be on W10 (here) or M15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!mmc_controller->slots[0].nomux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) omap_cfg_reg(MMC_DAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) omap_cfg_reg(MMC_DAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Block 2 is on newer chips, and has many pinout options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (cpu_is_omap16xx() && controller_nr == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!mmc_controller->slots[1].nomux) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) omap_cfg_reg(Y8_1610_MMC2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) omap_cfg_reg(Y10_1610_MMC2_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) omap_cfg_reg(R18_1610_MMC2_CLKIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) omap_cfg_reg(W8_1610_MMC2_DAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (mmc_controller->slots[1].wires == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) omap_cfg_reg(V8_1610_MMC2_DAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) omap_cfg_reg(W15_1610_MMC2_DAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) omap_cfg_reg(R10_1610_MMC2_DAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* These are needed for the level shifter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) omap_cfg_reg(V9_1610_MMC2_CMDDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) omap_cfg_reg(V5_1610_MMC2_DATDIR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) omap_cfg_reg(W19_1610_MMC2_DATDIR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Feedback clock must be set on OMAP-1710 MMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (cpu_is_omap1710())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MOD_CONF_CTRL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OMAP_MMC_NR_RES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Register MMC devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int __init omap_mmc_add(const char *name, int id, unsigned long base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long size, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned rx_req, unsigned tx_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct omap_mmc_platform_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct resource res[OMAP_MMC_NR_RES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pdev = platform_device_alloc(name, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) memset(res, 0, OMAP_MMC_NR_RES * sizeof(struct resource));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) res[0].start = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) res[0].end = base + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) res[0].flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) res[1].start = res[1].end = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) res[1].flags = IORESOURCE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) res[2].start = rx_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) res[2].name = "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) res[2].flags = IORESOURCE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) res[3].start = tx_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) res[3].name = "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) res[3].flags = IORESOURCE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) data->slots[0].features = MMC_OMAP7XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) data->slots[0].features = MMC_OMAP15XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) data->slots[0].features = MMC_OMAP16XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = platform_device_add_data(pdev, data, sizeof(*data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = platform_device_add(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* return device handle to board setup code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) data->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) platform_device_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int nr_controllers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < nr_controllers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned rx_req, tx_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!mmc_data[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) omap1_mmc_mux(mmc_data[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) base = OMAP1_MMC1_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) irq = INT_MMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rx_req = 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tx_req = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) base = OMAP1_MMC2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) irq = INT_1610_MMC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rx_req = 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tx_req = 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) size = OMAP1_MMC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) omap_mmc_add("mmci-omap", i, base, size, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rx_req, tx_req, mmc_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* OMAP7xx SPI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #if IS_ENABLED(CONFIG_SPI_OMAP_100K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct platform_device omap_spi1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "omap1_spi100k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct platform_device omap_spi2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "omap1_spi100k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void omap_init_spi100k(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (omap_spi1.dev.platform_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) platform_device_register(&omap_spi1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (omap_spi2.dev.platform_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) platform_device_register(&omap_spi2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline void omap_init_spi100k(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static inline void omap_init_sti(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Numbering for the SPI-capable controllers when used for SPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * spi = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * uwire = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * mmc1..2 = 3..4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * mcbsp1..3 = 5..7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #if IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OMAP_UWIRE_BASE 0xfffb3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct resource uwire_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .start = OMAP_UWIRE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .end = OMAP_UWIRE_BASE + 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct platform_device omap_uwire_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .name = "omap_uwire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .num_resources = ARRAY_SIZE(uwire_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .resource = uwire_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void omap_init_uwire(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* FIXME define and use a boot tag; not all boards will be hooking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * up devices to the microwire controller, and multi-board configs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * mean that CONFIG_SPI_OMAP_UWIRE may be configured anyway...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* board-specific code must configure chipselects (only a few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * are normally used) and SCLK/SDI/SDO (each has two choices).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (void) platform_device_register(&omap_uwire_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline void omap_init_uwire(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define OMAP1_RNG_BASE 0xfffe5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct resource omap1_rng_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .start = OMAP1_RNG_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .end = OMAP1_RNG_BASE + 0x4f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct platform_device omap1_rng_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "omap_rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .num_resources = ARRAY_SIZE(omap1_rng_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .resource = omap1_rng_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void omap1_init_rng(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (void) platform_device_register(&omap1_rng_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * This gets called after board-specific INIT_MACHINE, and initializes most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * on-chip peripherals accessible on this board (except for few like USB):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * (a) Does any "standard config" pin muxing needed. Board-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * code will have muxed GPIO pins and done "nonstandard" setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * that code could live in the boot loader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * (b) Populating board-specific platform_data with the data drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * rely on to handle wiring variations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * (c) Creating platform devices as meaningful on this board and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * with this kernel configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Claiming GPIOs, and setting their direction and initial values, is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * responsibility of the device drivers. So is responding to probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Board-specific knowledge like creating devices or pin setup is to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * kept out of drivers as much as possible. In particular, pin setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * may be handled by the boot loader, and drivers should expect it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * normally have been done by the time they're probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int __init omap1_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!cpu_class_is_omap1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) omap_sram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) omap1_clk_late_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* please keep these calls, and their implementations above,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * in alphabetical order so they're easier to sort through.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) omap_init_mbox();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) omap_init_rtc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) omap_init_spi100k();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) omap_init_sti();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) omap_init_uwire();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) omap1_init_rng();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) arch_initcall(omap1_init_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #if IS_ENABLED(CONFIG_OMAP_WATCHDOG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct resource wdt_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .start = 0xfffeb000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .end = 0xfffeb07F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct platform_device omap_wdt_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .name = "omap_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .num_resources = ARRAY_SIZE(wdt_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .resource = wdt_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int __init omap_init_wdt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct omap_wd_timer_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pdata.read_reset_sources = omap1_get_reset_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = platform_device_register(&omap_wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = platform_device_add_data(&omap_wdt_device, &pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sizeof(pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) platform_device_del(&omap_wdt_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) subsys_initcall(omap_init_wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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