^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap1/clock_data.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * To do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - Clocks that are only available on some chips should be marked with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * chips that they are present on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mach-types.h> /* for machine_is_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <mach/usb.h> /* for OTG_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "sram.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IDL_CLKOUT_ARM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IDLTIM_ARM_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IDLAPI_ARM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IDLIF_ARM_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IDLLB_ARM_SHIFT 4 /* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IDLPER_ARM_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IDLXORP_ARM_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IDLWDT_ARM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CONF_MOD_UART3_CLK_MODE_R 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CONF_MOD_UART2_CLK_MODE_R 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CONF_MOD_UART1_CLK_MODE_R 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CONF_MOD_MMC_SD_CLK_REQ_R 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CONF_MOD_MCBSP3_AUXON 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CONF_MOD_SOSSI_CLK_EN_R 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Some OTG_SYSCON_2-specific bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OTG_SYSCON_2_UHOST_EN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SOFT_MMC2_DPLL_REQ_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SOFT_MMC_DPLL_REQ_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SOFT_UART3_DPLL_REQ_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SOFT_UART2_DPLL_REQ_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SOFT_UART1_DPLL_REQ_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SOFT_CAM_DPLL_REQ_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SOFT_COM_MCKO_REQ_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define USB_REQ_EN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SOFT_DPLL_REQ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Omap1 clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct clk ck_ref = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .name = "ck_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct clk ck_dpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "ck_dpll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .parent = &ck_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * FIXME: This clock seems to be necessary but no-one has asked for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * activation. [ FIX: SoSSI, SSR ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct arm_idlect1_clk ck_dpll1out = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "ck_dpll1out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .enable_bit = EN_CKOUT_ARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct clk sossi_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .name = "ck_sossi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .parent = &ck_dpll1out.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .recalc = &omap1_sossi_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .set_rate = &omap1_set_sossi_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct clk arm_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "arm_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .rate_offset = CKCTL_ARMDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct arm_idlect1_clk armper_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "armper_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .enable_bit = EN_PERCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .rate_offset = CKCTL_PERDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .idlect_shift = IDLPER_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * FIXME: This clock seems to be necessary but no-one has asked for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * activation. [ GPIO code for 1510 ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct clk arm_gpio_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .enable_bit = EN_GPIOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct arm_idlect1_clk armxor_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "armxor_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .parent = &ck_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .enable_bit = EN_XORPCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .idlect_shift = IDLXORP_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct arm_idlect1_clk armtim_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "armtim_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .parent = &ck_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .enable_bit = EN_TIMCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .idlect_shift = IDLTIM_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct arm_idlect1_clk armwdt_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "armwdt_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .parent = &ck_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .enable_bit = EN_WDTCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .fixed_div = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .recalc = &omap_fixed_divisor_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .idlect_shift = IDLWDT_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct clk arminth_ck16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "arminth_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .parent = &arm_ck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Note: On 16xx the frequency can be divided by 2 by programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 1510 version is in TC clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct clk dsp_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "dsp_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .enable_bit = EN_DSPCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .rate_offset = CKCTL_DSPDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct clk dspmmu_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "dspmmu_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct clk dspper_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "dspper_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .ops = &clkops_dspck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .enable_reg = DSP_IDLECT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .enable_bit = EN_PERCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .rate_offset = CKCTL_PERDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .recalc = &omap1_ckctl_recalc_dsp_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .set_rate = &omap1_clk_set_rate_dsp_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static struct clk dspxor_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .name = "dspxor_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .ops = &clkops_dspck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .parent = &ck_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .enable_reg = DSP_IDLECT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .enable_bit = EN_XORPCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct clk dsptim_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "dsptim_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .ops = &clkops_dspck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .parent = &ck_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .enable_reg = DSP_IDLECT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .enable_bit = EN_DSPTIMCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct arm_idlect1_clk tc_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "tc_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .rate_offset = CKCTL_TCDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .idlect_shift = IDLIF_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct clk arminth_ck1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "arminth_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Note: On 1510 the frequency follows TC_CK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * 16xx version is in MPU clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct clk tipb_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* No-idle controlled by "tc_ck" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .name = "tipb_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct clk l3_ocpi_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* No-idle controlled by "tc_ck" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .name = "l3_ocpi_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .enable_bit = EN_OCPI_CK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct clk tc1_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "tc1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .enable_bit = EN_TC1_CK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * FIXME: This clock seems to be necessary but no-one has asked for its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * activation. [ pm.c (SRAM), CCP, Camera ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct clk tc2_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "tc2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .enable_bit = EN_TC2_CK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct clk dma_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* No-idle controlled by "tc_ck" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "dma_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct clk dma_lcdfree_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "dma_lcdfree_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct arm_idlect1_clk api_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .name = "api_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .enable_bit = EN_APICK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .idlect_shift = IDLAPI_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static struct arm_idlect1_clk lb_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .name = "lb_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .enable_bit = EN_LBCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .idlect_shift = IDLLB_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct clk rhea1_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "rhea1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct clk rhea2_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .name = "rhea2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .parent = &tc_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct clk lcd_ck_16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = "lcd_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .enable_bit = EN_LCDCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .rate_offset = CKCTL_LCDDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct arm_idlect1_clk lcd_ck_1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .name = "lcd_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .parent = &ck_dpll1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .flags = CLOCK_IDLE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .enable_bit = EN_LCDCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .rate_offset = CKCTL_LCDDIV_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .recalc = &omap1_ckctl_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .round_rate = omap1_clk_round_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .set_rate = omap1_clk_set_rate_ckctl_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * XXX The enable_bit here is misused - it simply switches between 12MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * and 48MHz. Reimplement with clksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * XXX does this need SYSC register handling?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct clk uart1_1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .name = "uart1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Direct from ULPD, no real parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .set_rate = &omap1_set_uart_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .recalc = &omap1_uart_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * XXX The enable_bit here is misused - it simply switches between 12MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * and 48MHz. Reimplement with clksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * XXX SYSC register handling does not belong in the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct uart_clk uart1_16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = "uart1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .ops = &clkops_uart_16xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Direct from ULPD, no real parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .sysc_addr = 0xfffb0054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * XXX The enable_bit here is misused - it simply switches between 12MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * and 48MHz. Reimplement with clksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * XXX does this need SYSC register handling?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct clk uart2_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .name = "uart2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Direct from ULPD, no real parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .set_rate = &omap1_set_uart_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .recalc = &omap1_uart_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * XXX The enable_bit here is misused - it simply switches between 12MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * and 48MHz. Reimplement with clksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * XXX does this need SYSC register handling?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct clk uart3_1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "uart3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Direct from ULPD, no real parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .set_rate = &omap1_set_uart_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .recalc = &omap1_uart_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * XXX The enable_bit here is misused - it simply switches between 12MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * and 48MHz. Reimplement with clksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * XXX SYSC register handling does not belong in the clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct uart_clk uart3_16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .name = "uart3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .ops = &clkops_uart_16xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Direct from ULPD, no real parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .sysc_addr = 0xfffb9854,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = "usb_clko",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Direct from ULPD, no parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .rate = 6000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .flags = ENABLE_REG_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .enable_bit = USB_MCLK_EN_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct clk usb_hhc_ck1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "usb_hhc_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Direct from ULPD, no parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .flags = ENABLE_REG_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .enable_bit = USB_HOST_HHC_UHOST_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct clk usb_hhc_ck16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .name = "usb_hhc_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Direct from ULPD, no parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .flags = ENABLE_REG_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct clk usb_dc_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "usb_dc_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Direct from ULPD, no parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct clk uart1_7xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .name = "uart1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Direct from ULPD, no parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .enable_bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct clk uart2_7xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .name = "uart2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* Direct from ULPD, no parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .enable_bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct clk mclk_1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .name = "mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Direct from ULPD, no parent. May be enabled by ext hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static struct clk mclk_16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .name = "mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Direct from ULPD, no parent. May be enabled by ext hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .enable_bit = COM_ULPD_PLL_CLK_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .set_rate = &omap1_set_ext_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .round_rate = &omap1_round_ext_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .init = &omap1_init_ext_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct clk bclk_1510 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .name = "bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Direct from ULPD, no parent. May be enabled by ext hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static struct clk bclk_16xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .name = "bclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Direct from ULPD, no parent. May be enabled by ext hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .enable_bit = SWD_ULPD_PLL_CLK_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .set_rate = &omap1_set_ext_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .round_rate = &omap1_round_ext_clk_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .init = &omap1_init_ext_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct clk mmc1_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = "mmc1_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Functional clock is direct from ULPD, interface clock is ARMPER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * CONF_MOD_MCBSP3_AUXON ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct clk mmc2_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .name = "mmc2_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Functional clock is direct from ULPD, interface clock is ARMPER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .enable_bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static struct clk mmc3_ck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .name = "mmc3_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .ops = &clkops_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Functional clock is direct from ULPD, interface clock is ARMPER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .rate = 48000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static struct clk virtual_ck_mpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .name = "mpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .parent = &arm_ck, /* Is smarter alias for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .set_rate = &omap1_select_table_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .round_rate = &omap1_round_to_table_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) remains active during MPU idle whenever this is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static struct clk i2c_fck = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .name = "i2c_fck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .flags = CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .parent = &armxor_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static struct clk i2c_ick = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "i2c_ick",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .ops = &clkops_null,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .flags = CLOCK_NO_IDLE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .parent = &armper_ck.clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .recalc = &followparent_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * clkdev integration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static struct omap_clk omap_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* non-ULPD clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* CK_GEN1 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* CK_GEN2 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* CK_GEN3 clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* ULPD clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Virtual clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static void __init omap1_show_rates(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int __init omap1_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct omap_clk *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int crystal_type = 0; /* Default 12 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #ifdef CONFIG_DEBUG_LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Resets some clocks that may be left on from bootloader,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * but leaves serial clocks on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) omap_writew(reg, SOFT_REQ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) omap_writew(0, SOFT_REQ_REG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* By default all idlect1 clocks are allowed to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) arm_idlect1_mask = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) clk_preinit(c->lk.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) cpu_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (cpu_is_omap1710())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) cpu_mask |= CK_1710;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (cpu_is_omap16xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cpu_mask |= CK_16XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (cpu_is_omap1510())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) cpu_mask |= CK_1510;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) cpu_mask |= CK_7XX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (cpu_is_omap310())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) cpu_mask |= CK_310;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (c->cpu & cpu_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) clkdev_add(&c->lk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) clk_register(c->lk.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Pointers to these clocks are needed by code in clock.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) api_ck_p = clk_get(NULL, "api_ck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ck_dpll1_p = clk_get(NULL, "ck_dpll1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ck_ref_p = clk_get(NULL, "ck_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ck_ref.rate = 13000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (cpu_is_omap16xx() && crystal_type == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ck_ref.rate = 19200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) omap_readw(ARM_CKCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* We want to be in syncronous scalable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) omap_writew(0x1000, ARM_SYSST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * Initially use the values set by bootloader. Determine PLL rate and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * recalculate dependent clocks as if kernel had changed PLL or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * divisors. See also omap1_clk_late_init() that can reprogram dpll1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * after the SRAM is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned pll_ctl_val = omap_readw(DPLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (pll_ctl_val & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* PLL enabled, apply multiplier and divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (pll_ctl_val & 0xf80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* PLL disabled, apply bypass divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) switch (pll_ctl_val & 0xc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case 0x4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ck_dpll1.rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ck_dpll1.rate /= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) propagate_rate(&ck_dpll1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Cache rates for clocks connected to ck_ref (not dpll1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) propagate_rate(&ck_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) omap1_show_rates();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Select slicer output as OMAP input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) OMAP7XX_PCC_UPLD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Amstrad Delta wants BCLK high when inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (machine_is_ams_delta())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) (1 << SDW_MCLK_INV_BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ULPD_CLOCK_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* (on 730, bit 13 must not be cleared) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (cpu_is_omap7xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* Put DSP/MPUI into reset until needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) omap_writew(0, ARM_RSTCT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) omap_writew(1, ARM_RSTCT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) omap_writew(0x400, ARM_IDLECT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * of the ARM_IDLECT2 register must be set to zero. The power-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * default value of this bit is one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Only enable those clocks we will need, let the drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * enable other clocks as necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) clk_enable(&armper_ck.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) clk_enable(&armxor_ck.clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) clk_enable(&armtim_ck.clk); /* This should be done by timer code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (cpu_is_omap15xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) clk_enable(&arm_gpio_ck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define OMAP1_DPLL1_SANE_VALUE 60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) void __init omap1_clk_late_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unsigned long rate = ck_dpll1.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Find the highest supported frequency and enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pr_err("System frequencies not set, using default. Check your config.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Reprogramming the DPLL is tricky, it must be done from SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) omap_sram_reprogram_clock(0x2290, 0x0005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) propagate_rate(&ck_dpll1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) omap1_show_rates();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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