Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mach-omap1/clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) struct omap_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	u16				cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct clk_lookup		lk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK(dev, con, ck, cp)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		 .cpu = cp,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.lk = {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			.dev_id = dev,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			.con_id = con,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			.clk = ck,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		},			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Platform flags for the clkdev-OMAP integration code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CK_310		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CK_7XX		(1 << 1)	/* 7xx, 850 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CK_1510		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CK_16XX		(1 << 3)	/* 16xx, 17xx, 5912 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CK_1710		(1 << 4)	/* 1710 extra for rate selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* Temporary, needed during the common clock framework conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define __clk_get_name(clk)	(clk->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define __clk_get_parent(clk)	(clk->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define __clk_get_rate(clk)	(clk->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * struct clkops - some clock function pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * @enable: fn ptr that enables the current clock in hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @disable: fn ptr that enables the current clock in hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @find_idlest: function returning the IDLEST register for the clock's IP blk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @find_companion: function returning the "companion" clk reg for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * A "companion" clk is an accompanying clock to the one being queried
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * that must be enabled for the IP module connected to the clock to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * become accessible by the hardware.  Neither @find_idlest nor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @find_companion should be needed; that information is IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * block-specific; the hwmod code has been created to handle this, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * until hwmod data is ready and drivers have been converted to use PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * @find_companion must, unfortunately, remain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct clkops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int			(*enable)(struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	void			(*disable)(struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	void			(*find_idlest)(struct clk *, void __iomem **,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 					       u8 *, u8 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	void			(*find_companion)(struct clk *, void __iomem **,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 						  u8 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	void			(*allow_idle)(struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	void			(*deny_idle)(struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * struct clk.flags possibilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * XXX document the rest of the clock flags here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *     bits share the same register.  This flag allows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *     should be used.  This is a temporary solution - a better approach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *     would be to associate clock type-specific data with the clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *     similar to the struct dpll_data approach.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLOCK_IDLE_CONTROL	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLOCK_NO_IDLE_PARENT	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLOCK_CLKOUTX2		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * struct clk - OMAP struct clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * @node: list_head connecting this clock into the full clock list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * @ops: struct clkops * for this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * @name: the name of the clock in the hardware (used in hwmod data and debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * @parent: pointer to this clock's parent struct clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * @children: list_head connecting to the child clks' @sibling list_heads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * @sibling: list_head connecting this clk to its parent clk's @children
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * @rate: current clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * @enable_reg: register to write to enable the clock (see @enable_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * @recalc: fn ptr that returns the clock's current rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * @set_rate: fn ptr that can change the clock's current rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * @round_rate: fn ptr that can round the clock's current rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * @init: fn ptr to do clock-specific initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * @usecount: number of users that have requested this clock to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * @flags: see "struct clk.flags possibilities" above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * @src_offset: bitshift for source selection bitfield (OMAP1 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * XXX @rate_offset, @src_offset should probably be removed and OMAP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * clock code converted to use clksel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * XXX @usecount is poorly named.  It should be "enable_count" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * something similar.  "users" in the description refers to kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * code (core code or drivers) that have called clk_enable() and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * yet called clk_disable(); the usecount of parent clocks is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * incremented by the clock code when clk_enable() is called on child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * clocks and decremented by the clock code when clk_disable() is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * called on child clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * XXX @clkdm, @usecount, @children, @sibling should be marked for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * internal use only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * @children and @sibling are used to optimize parent-to-child clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * tree traversals.  (child-to-parent traversals use @parent.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * XXX The notion of the clock's current rate probably needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  * separated from the clock's target rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct list_head	node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	const struct clkops	*ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	const char		*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct clk		*parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct list_head	children;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct list_head	sibling;	/* node for children */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long		rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	void __iomem		*enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned long		(*recalc)(struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int			(*set_rate)(struct clk *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	long			(*round_rate)(struct clk *, unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	void			(*init)(struct clk *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u8			enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	s8			usecount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u8			fixed_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8			flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u8			rate_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u8			src_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct dentry		*dent;	/* For visible tree hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct clk_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int		(*clk_enable)(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	void		(*clk_disable)(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	long		(*clk_round_rate)(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int		(*clk_set_rate)(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int		(*clk_set_parent)(struct clk *clk, struct clk *parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	void		(*clk_allow_idle)(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	void		(*clk_deny_idle)(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	void		(*clk_disable_unused)(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) extern int clk_init(struct clk_functions *custom_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) extern void clk_preinit(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern int clk_register(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) extern void clk_reparent(struct clk *child, struct clk *parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) extern void clk_unregister(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) extern void propagate_rate(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) extern void recalculate_root_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) extern unsigned long followparent_recalc(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) extern void clk_enable_init_clocks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long omap_fixed_divisor_recalc(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) extern struct clk *omap_clk_get_by_name(const char *name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) extern int omap_clk_enable_autoidle_all(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) extern int omap_clk_disable_autoidle_all(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) extern const struct clkops clkops_null;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) extern struct clk dummy_ck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int omap1_clk_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) void omap1_clk_late_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) extern int omap1_clk_enable(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) extern void omap1_clk_disable(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern unsigned long omap1_ckctl_recalc(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) extern unsigned long omap1_sossi_recalc(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) extern unsigned long omap1_uart_recalc(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) extern void omap1_init_ext_clk(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) extern unsigned long omap1_watchdog_recalc(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifdef CONFIG_OMAP_RESET_CLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) extern void omap1_clk_disable_unused(struct clk *clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define omap1_clk_disable_unused	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct uart_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct clk	clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned long	sysc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Provide a method for preventing idling some ARM IDLECT clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct arm_idlect1_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct clk	clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	unsigned long	no_idle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	__u8		idlect_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* ARM_CKCTL bit shifts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CKCTL_PERDIV_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CKCTL_LCDDIV_OFFSET	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CKCTL_ARMDIV_OFFSET	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CKCTL_DSPDIV_OFFSET	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CKCTL_TCDIV_OFFSET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CKCTL_DSPMMUDIV_OFFSET	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*#define ARM_TIMXO		12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EN_DSPCK		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*#define ARM_INTHCK_SEL	14*/ /* Divide-by-2 for mpu inth_ck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* DSP_CKCTL bit shifts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CKCTL_DSPPERDIV_OFFSET	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* ARM_IDLECT2 bit shifts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EN_WDTCK	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EN_XORPCK	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define EN_PERCK	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define EN_LCDCK	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EN_LBCK		4 /* Not on 1610/1710 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*#define EN_HSABCK	5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EN_APICK	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EN_TIMCK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DMACK_REQ	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define EN_GPIOCK	9 /* Not on 1610/1710 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*#define EN_LBFREECK	10*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EN_CKOUT_ARM	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* ARM_IDLECT3 bit shifts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EN_OCPI_CK	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define EN_TC1_CK	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EN_TC2_CK	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define EN_DSPTIMCK	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Various register defines for clock controls scattered around OMAP chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SDW_MCLK_INV_BIT	2	/* In ULPD_CLKC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define USB_MCLK_EN_BIT		4	/* In ULPD_CLKC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define USB_HOST_HHC_UHOST_EN	9	/* In MOD_CONF_CTRL_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SWD_ULPD_PLL_CLK_REQ	1	/* In SWD_CLK_DIV_CTRL_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define COM_ULPD_PLL_CLK_REQ	1	/* In COM_CLK_DIV_CTRL_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SWD_CLK_DIV_CTRL_SEL	0xfffe0874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define COM_CLK_DIV_CTRL_SEL	0xfffe0878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SOFT_REQ_REG		0xfffe0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SOFT_REQ_REG2		0xfffe0880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) extern __u32 arm_idlect1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) extern const struct clkops clkops_dspck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extern const struct clkops clkops_dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) extern const struct clkops clkops_uart_16xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) extern const struct clkops clkops_generic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* used for passing SoC type to omap1_{select,round_to}_table_rate() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) extern u32 cpu_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif