^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap1/board-fsample.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Modified from board-perseus2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Original OMAP730 support by Jean Pihet <j-pihet@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Updated for 2.6 by Kevin Hilman <kjh@hilman.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/platnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/omapfb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <mach/tc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "flash.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_data/keypad-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "fpga.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* fsample is pretty close to p2-sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define fsample_cpld_read(reg) __raw_readb(reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define fsample_cpld_write(val, reg) __raw_writeb(val, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSAMPLE_CPLD_BASE 0xE8100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSAMPLE_CPLD_SIZE SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FSAMPLE_CPLD_START 0x05080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FSAMPLE_CPLD_BIT_BT_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FSAMPLE_CPLD_BIT_LCD_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FSAMPLE_CPLD_BIT_CAM_PWDN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FSAMPLE_CPLD_BIT_BACKLIGHT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FSAMPLE_CPLD_BIT_OTG_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define fsample_cpld_set(bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define fsample_cpld_clear(bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const unsigned int fsample_keymap[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) KEY(0, 0, KEY_UP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) KEY(1, 0, KEY_RIGHT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) KEY(2, 0, KEY_LEFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) KEY(3, 0, KEY_DOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) KEY(4, 0, KEY_ENTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) KEY(0, 1, KEY_F10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) KEY(1, 1, KEY_SEND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) KEY(2, 1, KEY_END),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) KEY(3, 1, KEY_VOLUMEDOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) KEY(4, 1, KEY_VOLUMEUP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) KEY(5, 1, KEY_RECORD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) KEY(0, 2, KEY_F9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) KEY(1, 2, KEY_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) KEY(2, 2, KEY_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) KEY(3, 2, KEY_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) KEY(4, 2, KEY_KPDOT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) KEY(0, 3, KEY_BACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) KEY(1, 3, KEY_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) KEY(2, 3, KEY_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) KEY(3, 3, KEY_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) KEY(4, 3, KEY_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) KEY(5, 3, KEY_KPSLASH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) KEY(0, 4, KEY_HOME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) KEY(1, 4, KEY_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) KEY(2, 4, KEY_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) KEY(3, 4, KEY_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) KEY(4, 4, KEY_KPASTERISK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) KEY(5, 4, KEY_POWER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct smc91x_platdata smc91x_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .leda = RPC_LED_100_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ledb = RPC_LED_TX_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct resource smc91x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .end = H2P2_DBG_FPGA_ETHR_START + 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .start = INT_7XX_MPU_EXT_NIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .end = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void __init fsample_init_smc91x(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mdelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) H2P2_DBG_FPGA_LAN_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mdelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct mtd_partition nor_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* bootloader (U-Boot, etc) in first sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* bootloader params in the next sector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "params",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .size = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .mask_flags = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* rest of flash is a file system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mask_flags = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct physmap_flash_data nor_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .set_vpp = omap1_set_vpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .parts = nor_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .nr_parts = ARRAY_SIZE(nor_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct resource nor_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .start = OMAP_CS0_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .end = OMAP_CS0_PHYS + SZ_32M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct platform_device nor_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .platform_data = &nor_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .resource = &nor_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FSAMPLE_NAND_RB_GPIO_PIN 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int nand_dev_ready(struct nand_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct platform_nand_data nand_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .chip_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .options = NAND_SAMSUNG_LP_OPTIONS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .ctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .cmd_ctrl = omap1_nand_cmd_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .dev_ready = nand_dev_ready,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct resource nand_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .start = OMAP_CS3_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .end = OMAP_CS3_PHYS + SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_device nand_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "gen_nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .platform_data = &nand_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .resource = &nand_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct platform_device smc91x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .platform_data = &smc91x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .num_resources = ARRAY_SIZE(smc91x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .resource = smc91x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct resource kp_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .start = INT_7XX_MPUIO_KEYPAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .end = INT_7XX_MPUIO_KEYPAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct matrix_keymap_data fsample_keymap_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .keymap = fsample_keymap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .keymap_size = ARRAY_SIZE(fsample_keymap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct omap_kp_platform_data kp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .rows = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .cols = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .keymap_data = &fsample_keymap_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .delay = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct platform_device kp_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = "omap-keypad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .platform_data = &kp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_resources = ARRAY_SIZE(kp_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .resource = kp_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct platform_device *devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &nor_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &nand_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) &smc91x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) &kp_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct omap_lcd_config fsample_lcd_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .ctrl_name = "internal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void __init omap_fsample_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Early, board-dependent init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Hold GSM Reset until needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * UARTs -> done automagically by 8250 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * CSx timings, GPIO Mux ... setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Flash: CS0 timings setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * Ethernet support through the debug board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * CS1 timings setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * It is used as the Ethernet controller interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) OMAP7XX_IO_CONF_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) fsample_init_smc91x();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) BUG_ON(gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Mux pins for keypad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) omap_cfg_reg(E2_7XX_KBR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) omap_cfg_reg(J7_7XX_KBR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) omap_cfg_reg(E1_7XX_KBR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) omap_cfg_reg(F3_7XX_KBR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) omap_cfg_reg(D2_7XX_KBR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) omap_cfg_reg(C2_7XX_KBC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) omap_cfg_reg(D3_7XX_KBC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) omap_cfg_reg(E4_7XX_KBC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) omap_cfg_reg(F4_7XX_KBC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) omap_cfg_reg(E3_7XX_KBC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) platform_add_devices(devices, ARRAY_SIZE(devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) omap_serial_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) omap_register_i2c_bus(1, 100, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) omapfb_set_lcd_config(&fsample_lcd_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Only FPGA needs to be mapped here. All others are done with ioremap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct map_desc omap_fsample_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .virtual = H2P2_DBG_FPGA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .length = H2P2_DBG_FPGA_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .virtual = FSAMPLE_CPLD_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .pfn = __phys_to_pfn(FSAMPLE_CPLD_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .length = FSAMPLE_CPLD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void __init omap_fsample_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) omap15xx_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) iotable_init(omap_fsample_io_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ARRAY_SIZE(omap_fsample_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Maintainer: Brian Swetland <swetland@google.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .map_io = omap_fsample_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .init_early = omap1_init_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .init_irq = omap1_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .handle_irq = omap1_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .init_machine = omap_fsample_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .init_late = omap1_init_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .init_time = omap1_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .restart = omap1_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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