^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amstrad E3 FIQ handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Janusz Krzysztofik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2006 Matt Callow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2004 Amstrad Plc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001 RidgeRun, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/ams-delta-fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "ams-delta-fiq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "board-ams-delta.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct fiq_handler fh = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .name = "ams-delta-fiq"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * This buffer is shared between FIQ and IRQ contexts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The FIQ and IRQ isrs can both read and write it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * It is structured as a header section several 32bit slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * followed by the circular buffer where the FIQ isr stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * keystrokes received from the qwerty keyboard. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static unsigned int fiq_buffer[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct irq_data *irq_data[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static unsigned int irq_counter[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char *pin_name[16] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [AMS_DELTA_GPIO_PIN_KEYBRD_DATA] = "keybrd_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) [AMS_DELTA_GPIO_PIN_KEYBRD_CLK] = "keybrd_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static irqreturn_t deferred_fiq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct irq_data *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int gpio, irq_num, fiq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * For each handled GPIO interrupt, keep calling its interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * until the IRQ counter catches the FIQ incremented interrupt counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) d = irq_data[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) irq_num = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (irq_counter[gpio] < fiq_count &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * handle_simple_irq() that OMAP GPIO edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * interrupts default to since commit 80ac93c27441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * requires interrupt already acked and unmasked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!WARN_ON_ONCE(!irq_chip->irq_unmask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) irq_chip->irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) generic_handle_irq(irq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void __init ams_delta_init_fiq(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct platform_device *serio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct gpio_desc *gpiod, *data = NULL, *clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void *fiqhandler_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int fiqhandler_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pt_regs FIQ_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long val, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int i, retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Store irq_chip location for IRQ handler use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irq_chip = chip->irq.chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!irq_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pr_err("%s: GPIO chip %s is missing IRQ function\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) chip->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < ARRAY_SIZE(irq_data); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) gpiod = gpiochip_request_own_desc(chip, i, pin_name[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GPIO_ACTIVE_HIGH, GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ERR(gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pr_err("%s: failed to get GPIO pin %d (%ld)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __func__, i, PTR_ERR(gpiod));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Store irq_data location for IRQ handler use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) irq_data[i] = irq_get_irq_data(gpiod_to_irq(gpiod));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * FIQ handler takes full control over serio data and clk GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * pins. Initialize them and keep requested so nobody can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * interfere. Fail if any of those two couldn't be requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case AMS_DELTA_GPIO_PIN_KEYBRD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) data = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) gpiod_direction_input(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case AMS_DELTA_GPIO_PIN_KEYBRD_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clk = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gpiod_direction_input(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) gpiochip_free_own_desc(gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!data || !clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto out_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) fiqhandler_start = &qwerty_fiqin_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_info("Installing fiq handler from %p, length 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) fiqhandler_start, fiqhandler_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) retval = claim_fiq(&fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) goto out_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (retval < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) release_fiq(&fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto out_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Since no set_type() method is provided by OMAP irq chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * switch to edge triggered interrupt type manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) offset = IRQ_ILR0_REG_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) set_fiq_handler(fiqhandler_start, fiqhandler_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Initialise the buffer which is shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * between FIQ mode and IRQ mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) fiq_buffer[FIQ_MASK] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) fiq_buffer[FIQ_STATE] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) fiq_buffer[FIQ_KEY] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) fiq_buffer[FIQ_KEYS_CNT] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) fiq_buffer[FIQ_KEYS_HICNT] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) fiq_buffer[FIQ_TAIL_OFFSET] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) fiq_buffer[FIQ_HEAD_OFFSET] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) fiq_buffer[FIQ_BUF_LEN] = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fiq_buffer[FIQ_MISSED_KEYS] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) fiq_buffer[FIQ_BUFFER_START] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fiq_buffer[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * FIQ mode r9 always points to the fiq_buffer, because the FIQ isr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * only means of communication with the IRQ level and other kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * context code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) set_fiq_regs(&FIQ_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Redirect GPIO interrupts to FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val = omap_readl(OMAP_IH1_BASE + offset) | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) omap_writel(val, OMAP_IH1_BASE + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Initialize serio device IRQ resource and platform_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) serio->resource[0].start = gpiod_to_irq(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) serio->resource[0].end = serio->resource[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) serio->dev.platform_data = fiq_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Since FIQ handler performs handling of GPIO registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * "keybrd_clk" IRQ pin, ams_delta_serio driver used to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * handle_simple_irq() as active IRQ handler for that pin to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * bad interaction with gpio-omap driver. This is no longer needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * as handle_simple_irq() is now the default handler for OMAP GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * edge interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * This comment replaces the obsolete code which has been removed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * from the ams_delta_serio driver and stands here only as a reminder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * of that dependency on gpio-omap driver behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) out_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) gpiochip_free_own_desc(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) gpiochip_free_own_desc(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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