^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on linux/arch/arm/lib/floppydma.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Renamed and modified to work with 2.6 kernel by Matt Callow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1995, 1996 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2004 Pete Trapps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2006 Matt Callow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2010 Janusz Krzysztofik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_data/ams-delta-fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_data/gpio-omap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "ams-delta-fiq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "board-ams-delta.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "iomap.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Unfortunately, it was not placed in a separate header file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OMAP1510_GPIO_BASE 0xFFFCE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* GPIO register bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OTHERS_MASK (MODEM_IRQ_MASK | HOOK_SWITCH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* IRQ handler register bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Driver buffer byte offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BUF_MASK (FIQ_MASK * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BUF_STATE (FIQ_STATE * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BUF_BUF_LEN (FIQ_BUF_LEN * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BUF_KEY (FIQ_KEY * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BUF_BUFFER_START (FIQ_BUFFER_START * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Register usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * r8 - temporary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * r9 - the driver buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * r10 - temporary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * r11 - interrupts mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * r12 - base pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * r13 - interrupts status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .global qwerty_fiqin_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ENTRY(qwerty_fiqin_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) @ FIQ intrrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ldr r12, omap_ih1_base @ set pointer to level1 handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) bics r13, r13, r11 @ clear masked - any left?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) beq exit @ none - spurious FIQ? exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mov r8, #2 @ reset FIQ agreement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) beq gpio @ yes - process it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mov r8, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) orr r8, r11, r8, lsl r10 @ mask spurious interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) str r8, [r12, #IRQ_MIR_REG_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) subs pc, lr, #4 @ return from FIQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) @@@@@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) gpio: @ GPIO bank interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) restart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bics r13, r13, r11 @ clear masked - any left?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) beq exit @ no - spurious interrupt? exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) orr r11, r11, r13 @ mask all requested interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) str r11, [r12, #OMAP1510_GPIO_INT_MASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) str r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack all requested interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) beq hksw @ no - try next source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) @@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) @ Keyboard clock FIQ mode interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) @ r10 now contains KEYBRD_CLK_MASK, use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bic r11, r11, r10 @ unmask it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) str r11, [r12, #OMAP1510_GPIO_INT_MASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) @ Process keyboard data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cmp r10, #0 @ are we expecting start bit?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bne data @ no - go to data processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) beq hksw @ no - try next source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) @ r8 contains KEYBRD_DATA_MASK, use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) str r8, [r9, #BUF_STATE] @ enter data processing state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) @ r10 already contains 0, reuse it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) str r10, [r9, #BUF_KEY] @ clear keycode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mov r10, #2 @ reset input bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) str r10, [r9, #BUF_MASK]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) @ Mask other GPIO line interrupts till key done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) b restart @ restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) @ r8 still contains GPIO input bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) orreq r8, r8, r10 @ set 1 at current mask position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) streq r8, [r9, #BUF_KEY] @ and save back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mov r10, r10, lsl #1 @ shift mask left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bics r10, r10, #0x800 @ have we got all the bits?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) strne r10, [r9, #BUF_MASK] @ not yet - store the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) bne restart @ and restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) @ r10 already contains 0, reuse it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) str r10, [r9, #BUF_STATE] @ reset state to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) @ Key done - restore interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) and r11, r11, r10 @ unmask all saved as unmasked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) @ Try appending the keycode to the circular buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cmp r10, r8 @ is buffer full?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) beq hksw @ yes - key lost, next source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) add r10, r10, #1 @ incremet keystrokes counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) str r10, [r9, #BUF_KEYS_CNT]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) @ r8 already contains buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cmp r10, r8 @ end of buffer?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) moveq r10, #0 @ yes - rewind to buffer start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) add r12, r12, r10, LSL #2 @ calculate buffer tail address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ldr r8, [r9, #BUF_KEY] @ get last keycode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) str r8, [r12] @ append it to the buffer tail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) add r10, r10, #1 @ increment buffer tail offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) str r10, [r9, #BUF_TAIL_OFFSET]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) add r10, r10, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) str r10, [r9, #BUF_CNT_INT_KEY]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) @@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) hksw: @Is hook switch interrupt requested?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) beq mdm @ no - try next source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) @@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) @ Hook switch interrupt FIQ mode simple handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) @ Don't toggle active edge, the switch always bounces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) @ Increment hook switch interrupt counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ldr r10, [r9, #BUF_CNT_INT_HSW]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) add r10, r10, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) str r10, [r9, #BUF_CNT_INT_HSW]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) @@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mdm: @Is it a modem interrupt?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tst r13, #MODEM_IRQ_MASK @ is modem status bit set?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) beq irq @ no - check for next interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) @@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) @ Modem FIQ mode interrupt handler stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) @ Increment modem interrupt counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ldr r10, [r9, #BUF_CNT_INT_MDM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) add r10, r10, #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) str r10, [r9, #BUF_CNT_INT_MDM]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) @@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) irq: @ Place deferred_fiq interrupt request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) b restart @ check for next GPIO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) @@@@@@@@@@@@@@@@@@@@@@@@@@@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Virtual addresses for IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) omap_ih1_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .word OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) deferred_fiq_ih_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) omap1510_gpio_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) qwerty_fiqin_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Check the size of the FIQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * it cannot go beyond 0xffff0200, and is copied to 0xffff001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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