Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) // Copyright (c) 2018 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright 2018 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NPCM7XX_SCRPAD_REG 0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern void npcm7xx_secondary_startup(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int npcm7xx_smp_boot_secondary(unsigned int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 				      struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	struct device_node *gcr_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	void __iomem *gcr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	if (!gcr_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		pr_err("no gcr device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	gcr_base = of_iomap(gcr_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	if (!gcr_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		pr_err("could not iomap gcr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* give boot ROM kernel start address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		  NPCM7XX_SCRPAD_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	/* make sure the previous write is seen by all observers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	dsb_sev();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	iounmap(gcr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct device_node *scu_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (!scu_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		pr_err("no scu device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	scu_base = of_iomap(scu_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	if (!scu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		pr_err("could not iomap scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	iounmap(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct smp_operations npcm7xx_smp_ops __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	.smp_prepare_cpus = npcm7xx_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	.smp_boot_secondary = npcm7xx_smp_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);