^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Yehuda Yitschak <yehuday@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory Clement <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The Armada 370 and Armada XP SOCs have a power management service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * unit which is responsible for powering down and waking up CPUs and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * other SOC units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define pr_fmt(fmt) "mvebu-pmsu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mvebu-pmsu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/cp15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "pmsu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PMSU_BASE_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PMSU_REG_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PMSU MP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* PMSU fabric registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define L2C_NFABRIC_PM_CTL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* PMSU delay registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PMSU_POWERDOWN_DELAY 0xF04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PMSU_POWERDOWN_DELAY_PMU BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PMSU_DFLT_ARMADA38X_DELAY 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* CA9 MPcore SoC Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MPCORE_RESET_CTL 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MPCORE_RESET_CTL_L2 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPCORE_RESET_CTL_DEBUG BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SRAM_PHYS_BASE 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BOOTROM_BASE 0xFFF00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BOOTROM_SIZE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ARMADA_370_CRYPT0_ENG_TARGET 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ARMADA_370_CRYPT0_ENG_ATTR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern void ll_disable_coherency(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern void ll_enable_coherency(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) extern void armada_370_xp_cpu_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern void armada_38x_cpu_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static phys_addr_t pmsu_mp_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void __iomem *pmsu_mp_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void *mvebu_cpu_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct of_device_id of_pmsu_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { .compatible = "marvell,armada-370-pmsu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { .compatible = "marvell,armada-370-xp-pmsu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { .compatible = "marvell,armada-380-pmsu", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { /* end of list */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(__pa_symbol(boot_addr), pmsu_mp_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) extern unsigned char mvebu_boot_wa_start[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern unsigned char mvebu_boot_wa_end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * This function sets up the boot address workaround needed for SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * BootROM Mbus window, and instead remaps a crypto SRAM into which a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * custom piece of code is copied to replace the problematic BootROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int crypto_eng_attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) phys_addr_t resume_addr_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void __iomem *sram_virt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SRAM_PHYS_BASE, SZ_64K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!sram_virt_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_err("Unable to map SRAM to setup the boot address WA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * The last word of the code copied in SRAM must contain the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * physical base address of the PMSU register. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * intentionally store this address in the native endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * of the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __raw_writel((unsigned long)resume_addr_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sram_virt_base + code_len - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) iounmap(sram_virt_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int __init mvebu_v7_pmsu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) np = of_find_matching_node(NULL, of_pmsu_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pr_info("Initializing Power Management Service Unit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (of_address_to_resource(np, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pr_err("unable to get resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pr_warn(FW_WARN "deprecated pmsu binding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) res.start = res.start - PMSU_BASE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) res.end = res.start + PMSU_REG_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!request_mem_region(res.start, resource_size(&res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) np->full_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pr_err("unable to request region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pmsu_mp_phys_base = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pmsu_mp_base = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!pmsu_mp_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_err("unable to map registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) release_mem_region(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (pmsu_mp_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum pmsu_idle_prepare_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PMSU_PREPARE_NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PMSU_PREPARE_DEEP_IDLE = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* No locking is needed because we only access per-CPU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (pmsu_mp_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Adjust the PMSU configuration to wait for WFI signal, enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * IRQ and FIQ as wakeup events, set wait for snoop queue empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * indication and mask IRQ and FIQ from CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PMSU_STATUS_AND_MASK_IRQ_WAKEUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PMSU_STATUS_AND_MASK_FIQ_WAKEUP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PMSU_STATUS_AND_MASK_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PMSU_STATUS_AND_MASK_FIQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* ask HW to power down the L2 Cache if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (flags & PMSU_PREPARE_DEEP_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* request power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Disable snoop disable by HW - SW is taking care of it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (deepidle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) flags |= PMSU_PREPARE_DEEP_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = mvebu_v7_pmsu_idle_prepare(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) v7_exit_coherency_flush(all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ll_disable_coherency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* If we are here, wfi failed. As processors run out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * coherency for some time, tlbs might be stale, so flush them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) local_flush_tlb_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ll_enable_coherency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Test the CR_C bit and set it if it was cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "mrc p15, 0, r0, c1, c0, 0 \n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "tst r0, %0 \n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "orreq r0, r0, #(1 << 2) \n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "mcreq p15, 0, r0, c1, c0, 0 \n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "isb "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) : : "Ir" (CR_C) : "r0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pr_debug("Failed to suspend the system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int armada_370_xp_cpu_suspend(unsigned long deepidle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int armada_38x_do_cpu_suspend(unsigned long deepidle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (deepidle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) flags |= PMSU_PREPARE_DEEP_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mvebu_v7_pmsu_idle_prepare(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Already flushed cache, but do it again as the outer cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * functions dirty the cache with spinlocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) v7_exit_coherency_flush(louis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int armada_38x_cpu_suspend(unsigned long deepidle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return cpu_suspend(false, armada_38x_do_cpu_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* No locking is needed because we only access per-CPU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void mvebu_v7_pmsu_idle_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (pmsu_mp_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* cancel ask HW to power down the L2 Cache if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* cancel Enable wakeup events and mask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long action, void *hcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (action == CPU_PM_ENTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else if (action == CPU_PM_EXIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mvebu_v7_pmsu_idle_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static struct notifier_block mvebu_v7_cpu_pm_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .notifier_call = mvebu_v7_cpu_pm_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct platform_device mvebu_v7_cpuidle_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int broken_idle(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (of_property_read_bool(np, "broken-idle")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pr_warn("CPU idle is currently broken: disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static __init int armada_370_cpuidle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) phys_addr_t redirect_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (broken_idle(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * On Armada 370, there is "a slow exit process from the deep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * idle state due to heavy L1/L2 cache cleanup operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * performed by the BootROM software". To avoid this, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * replace the restart code of the bootrom by a a simple jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * to the boot address. Then the code located at this boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * address will take care of the initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ARMADA_370_CRYPT0_ENG_ATTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) redirect_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mvebu_cpu_resume = armada_370_xp_cpu_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static __init int armada_38x_cpuidle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) void __iomem *mpsoc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "marvell,armada-380-coherency-fabric");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (broken_idle(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "marvell,armada-380-mpcore-soc-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mpsoc_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) BUG_ON(!mpsoc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Set up reset mask when powering down the cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) reg = readl(mpsoc_base + MPCORE_RESET_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) reg |= MPCORE_RESET_CTL_L2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) reg |= MPCORE_RESET_CTL_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) writel(reg, mpsoc_base + MPCORE_RESET_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) iounmap(mpsoc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Set up delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reg &= ~PMSU_POWERDOWN_DELAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) reg |= PMSU_DFLT_ARMADA38X_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg |= PMSU_POWERDOWN_DELAY_PMU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) mvebu_cpu_resume = armada_38x_cpu_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static __init int armada_xp_cpuidle_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (broken_idle(np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mvebu_cpu_resume = armada_370_xp_cpu_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int __init mvebu_v7_cpu_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) np = of_find_matching_node(NULL, of_pmsu_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * Currently the CPU idle support for Armada 38x is broken, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * the CPU hotplug uses some of the CPU idle functions it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * broken too, so let's disable it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (of_machine_is_compatible("marvell,armada380")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) cpu_hotplug_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (of_machine_is_compatible("marvell,armadaxp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = armada_xp_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) else if (of_machine_is_compatible("marvell,armada370"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = armada_370_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else if (of_machine_is_compatible("marvell,armada380"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = armada_38x_cpuidle_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mvebu_v7_pmsu_enable_l2_powerdown_onidle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (mvebu_v7_cpuidle_device.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) platform_device_register(&mvebu_v7_cpuidle_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) arch_initcall(mvebu_v7_cpu_pm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) early_initcall(mvebu_v7_pmsu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void mvebu_pmsu_dfs_request_local(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Prepare to enter idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PMSU_STATUS_AND_MASK_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PMSU_STATUS_AND_MASK_FIQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Request the DFS transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* The fact of entering idle will trigger the DFS transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * We're back from idle, the DFS transition has completed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * clear the idle wait indication.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int mvebu_pmsu_dfs_request(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int hwcpu = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Clear any previous DFS DONE event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Mask the DFS done interrupt, since we are going to poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Trigger the DFS on the appropriate CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Poll until the DFS done event is generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) timeout = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Restore the DFS mask to its original state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags