^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Suspend/resume support. Currently supporting Armada XP only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/outercache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "coherency.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "pmsu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDRAM_CONFIG_OFFS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SDRAM_CONFIG_SR_MODE_BIT BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDRAM_OPERATION_OFFS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SDRAM_OPERATION_SELF_REFRESH 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SDRAM_DLB_EVICTION_OFFS 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDRAM_DLB_EVICTION_THRESHOLD_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void (*mvebu_board_pm_enter)(void __iomem *sdram_reg, u32 srcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void __iomem *sdram_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int mvebu_pm_powerdown(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 reg, srcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) outer_flush_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Issue a Data Synchronization Barrier instruction to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * that all state saving has been completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Flush the DLB and wait ~7 usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) reg = readl(sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reg &= ~SDRAM_DLB_EVICTION_THRESHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) udelay(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Set DRAM in battery backup mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) reg = readl(sdram_ctrl + SDRAM_CONFIG_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg &= ~SDRAM_CONFIG_SR_MODE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Prepare to go to self-refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) srcmd = readl(sdram_ctrl + SDRAM_OPERATION_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) srcmd &= ~0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) srcmd |= SDRAM_OPERATION_SELF_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mvebu_board_pm_enter(sdram_ctrl + SDRAM_OPERATION_OFFS, srcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BOOT_INFO_ADDR 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BOOT_MAGIC_WORD 0xdeadb002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BOOT_MAGIC_LIST_END 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Those registers are accessed before switching the internal register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * base, which is why we hardcode the 0xd0000000 base address, the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * used by the SoC out of reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MBUS_WINDOW_12_CTRL 0xd00200b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MBUS_INTERNAL_REG_ADDRESS 0xd0020080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SDRAM_WIN_BASE_REG(x) (0x20180 + (0x8*x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SDRAM_WIN_CTRL_REG(x) (0x20184 + (0x8*x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static phys_addr_t mvebu_internal_reg_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __be32 in_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) np = of_find_node_by_name(NULL, "internal-regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BUG_ON(!np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Ask the DT what is the internal register address on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * platform. In the mvebu-mbus DT binding, 0xf0010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * corresponds to the internal register window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) in_addr[0] = cpu_to_be32(0xf0010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) in_addr[1] = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return of_translate_address(np, in_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void mvebu_pm_store_armadaxp_bootinfo(u32 *store_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) phys_addr_t resume_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) resume_pc = __pa_symbol(armada_370_xp_cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * The bootloader expects the first two words to be a magic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * value (BOOT_MAGIC_WORD), followed by the address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * resume code to jump to. Then, it expects a sequence of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * (address, value) pairs, which can be used to restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * value of certain registers. This sequence must end with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * BOOT_MAGIC_LIST_END magic value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(BOOT_MAGIC_WORD, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(resume_pc, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Some platforms remap their internal register base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * to 0xf1000000. However, out of reset, window 12 starts at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 0xf0000000 and ends at 0xf7ffffff, which would overlap with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * the internal registers. Therefore, disable window 12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(MBUS_WINDOW_12_CTRL, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(0x0, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Set the internal register base address to the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * expected by Linux, as read from the Device Tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writel(mvebu_internal_reg_base(), store_addr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Ask the mvebu-mbus driver to store the SDRAM window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * configuration, which has to be restored by the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * before re-entering the kernel on resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) store_addr += mvebu_mbus_save_cpu_target(store_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(BOOT_MAGIC_LIST_END, store_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int mvebu_pm_store_bootinfo(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 *store_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) store_addr = phys_to_virt(BOOT_INFO_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (of_machine_is_compatible("marvell,armadaxp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mvebu_pm_store_armadaxp_bootinfo(store_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int mvebu_enter_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = mvebu_pm_store_bootinfo();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cpu_pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cpu_suspend(0, mvebu_pm_powerdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) outer_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mvebu_v7_pmsu_idle_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) set_cpu_coherent();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cpu_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int mvebu_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pr_warn("Entering suspend to RAM. Only special wake-up sources will resume the system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return mvebu_enter_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int mvebu_pm_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (state == PM_SUSPEND_STANDBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (state == PM_SUSPEND_MEM && mvebu_board_pm_enter != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct platform_suspend_ops mvebu_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .enter = mvebu_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .valid = mvebu_pm_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int __init mvebu_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!of_machine_is_compatible("marvell,armadaxp") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) !of_machine_is_compatible("marvell,armada370") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) !of_machine_is_compatible("marvell,armada380") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) !of_machine_is_compatible("marvell,armada390"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) suspend_set_ops(&mvebu_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) late_initcall(mvebu_pm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int __init mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 srcmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "marvell,armada-xp-sdram-controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (of_address_to_resource(np, 0, &res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!request_mem_region(res.start, resource_size(&res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) np->full_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) sdram_ctrl = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!sdram_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) release_mem_region(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mvebu_board_pm_enter = board_pm_enter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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