^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Board-level suspend/resume support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014-2015 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARMADA_PIC_NR_GPIOS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void __iomem *gpio_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int pic_gpios[ARMADA_PIC_NR_GPIOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 reg, ackcmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Put 001 as value on the GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reg = readl(gpio_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) reg &= ~BIT(pic_raw_gpios[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) reg |= BIT(pic_raw_gpios[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writel(reg, gpio_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Prepare writing 111 to the GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ackcmd = readl(gpio_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ackcmd |= BIT(pic_raw_gpios[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) srcmd = cpu_to_le32(srcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ackcmd = cpu_to_le32(ackcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Wait a while, the PIC needs quite a bit of time between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * two GPIO commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mdelay(3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Align to a cache line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ".balign 32\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Enter self refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "str %[srcmd], [%[sdram_reg]]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Wait 100 cycles for DDR to enter self refresh, by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * doing 50 times two instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "mov r1, #50\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "1: subs r1, r1, #1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "bne 1b\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Issue the command ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "str %[ackcmd], [%[gpio_ctrl]]\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Trap the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "b .\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) : : [srcmd] "r" (srcmd), [sdram_reg] "r" (sdram_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int __init mvebu_armada_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device_node *gpio_ctrl_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!of_machine_is_compatible("marvell,axp-gp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) np = of_find_node_by_name(NULL, "pm_pic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (pic_gpios[i] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) name = kasprintf(GFP_KERNEL, "pic-pin%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = gpio_request(pic_gpios[i], name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = gpio_direction_output(pic_gpios[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gpio_free(pic_gpios[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) i, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) gpio_free(pic_gpios[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) kfree(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (gpio_ctrl_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) of_node_put(gpio_ctrl_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) gpio_ctrl_np = args.np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pic_raw_gpios[i] = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) gpio_ctrl = of_iomap(gpio_ctrl_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!gpio_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mvebu_pm_suspend_init(mvebu_armada_pm_enter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) of_node_put(gpio_ctrl_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Registering the mvebu_board_pm_enter callback must be done before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the platform_suspend_ops will be registered. In the same time we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * also need to have the gpio devices registered. That's why we use a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * device_initcall_sync which is called after all the device_initcall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * (used by the gpio device) but before the late_initcall (used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * register the platform_suspend_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) device_initcall_sync(mvebu_armada_pm_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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