Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Symmetric Multi Processing (SMP) support for Armada XP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Lior Amsalem <alior@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Yehuda Yitschak <yehuday@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * This file implements the routines for preparing the SMP infrastructure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * and waking up the secondary CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "armada-370-xp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "pmsu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "coherency.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ARMADA_XP_MAX_CPUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define AXP_BOOTROM_BASE 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define AXP_BOOTROM_SIZE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct clk *boot_cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static struct clk *get_cpu_clk(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct clk *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct device_node *np = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	if (WARN(!np, "missing cpu node\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	cpu_clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (WARN_ON(IS_ERR(cpu_clk)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int ret, hw_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	pr_info("Booting CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	hw_cpu = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 * This is needed to wake up CPUs in the offline state after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	 * using CPU hotplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * This is needed to take secondary CPUs out of reset on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 * initial boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ret = mvebu_cpu_reset_deassert(hw_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		pr_warn("unable to boot CPU: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * When a CPU is brought back online, either through CPU hotplug, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * because of the boot of a kexec'ed kernel, the PMSU configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * for this CPU might be in the deep idle state, preventing this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * from receiving interrupts. Here, we therefore take out the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * CPU from this state, which was entered by armada_xp_cpu_die()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void armada_xp_secondary_init(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	mvebu_v7_pmsu_idle_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void __init armada_xp_smp_init_cpus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	unsigned int ncores = num_possible_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		panic("Invalid number of CPUs in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int armada_xp_sync_secondary_clk(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct clk *cpu_clk = get_cpu_clk(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!cpu_clk || !boot_cpu_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	clk_prepare_enable(cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	set_cpu_coherent();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	boot_cpu_clk = get_cpu_clk(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (boot_cpu_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		clk_prepare_enable(boot_cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					  "arm/mvebu/sync_clocks:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 					  armada_xp_sync_secondary_clk, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * In order to boot the secondary CPUs we need to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 * the bootROM is mapped at the correct address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		panic("Cannot find 'marvell,bootrom' compatible node");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	err = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		panic("Cannot get 'bootrom' node address");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (res.start != AXP_BOOTROM_BASE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	    resource_size(&res) != AXP_BOOTROM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		panic("The address for the BootROM is incorrect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void armada_xp_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * CPU hotplug is implemented by putting offline CPUs into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * deep idle sleep state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	armada_370_xp_pmsu_idle_enter(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * We need a dummy function, so that platform_can_cpu_hotplug() knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * we support CPU hotplug. However, the function does not need to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * anything, because CPUs going offline can enter the deep idle state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * by themselves, without any help from a still alive CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int armada_xp_cpu_kill(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const struct smp_operations armada_xp_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.smp_init_cpus		= armada_xp_smp_init_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.smp_prepare_cpus	= armada_xp_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.smp_boot_secondary	= armada_xp_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.smp_secondary_init     = armada_xp_secondary_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.cpu_die		= armada_xp_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.cpu_kill               = armada_xp_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		      &armada_xp_smp_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MV98DX3236_CPU_RESUME_CTRL_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MV98DX3236_CPU_RESUME_ADDR_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct of_device_id of_mv98dx3236_resume_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.compatible = "marvell,98dx3336-resume-ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ /* end of list */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	WARN_ON(hw_cpu != 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	base = of_io_request_and_map(np, 0, of_node_full_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int ret, hw_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	hw_cpu = cpu_logical_map(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					    armada_xp_secondary_startup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * This is needed to wake up CPUs in the offline state after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * using CPU hotplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * This is needed to take secondary CPUs out of reset on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * initial boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = mvebu_cpu_reset_deassert(hw_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		pr_warn("unable to boot CPU: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct smp_operations mv98dx3236_smp_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.smp_init_cpus		= armada_xp_smp_init_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.smp_prepare_cpus	= armada_xp_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.smp_boot_secondary	= mv98dx3236_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.smp_secondary_init     = armada_xp_secondary_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.cpu_die		= armada_xp_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.cpu_kill               = armada_xp_cpu_kill,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		      &mv98dx3236_smp_ops);