Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Device Tree support for Armada 370 and XP platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Lior Amsalem <alior@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Gregory CLEMENT <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/smp_scu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "armada-370-xp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "coherency.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "mvebu-soc-id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static void __iomem *scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Enables the SCU when available. Obviously, this is only useful on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * Cortex-A based SOCs, not on PJ4B based ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static void __init mvebu_scu_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct device_node *np =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		scu_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		scu_enable(scu_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) void __iomem *mvebu_get_scu_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return scu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * When returning from suspend, the platform goes through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * bootloader, which executes its DDR3 training code. This code has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * the unfortunate idea of using the first 10 KB of each DRAM bank to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * exercise the RAM and calculate the optimal timings. Therefore, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * area of RAM is overwritten, and shouldn't be used by the kernel if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * suspend/resume is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int __init mvebu_scan_mem(unsigned long node, const char *uname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				 int depth, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	const __be32 *reg, *endp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (type == NULL || strcmp(type, "memory"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (reg == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		reg = of_get_flat_dt_prop(node, "reg", &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (reg == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	endp = reg + (l / sizeof(__be32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		u64 base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		base = dt_mem_next_cell(dt_root_addr_cells, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		size = dt_mem_next_cell(dt_root_size_cells, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static void __init mvebu_memblock_reserve(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	of_scan_flat_dt(mvebu_scan_mem, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void __init mvebu_memblock_reserve(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void __init mvebu_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	irqchip_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mvebu_scu_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	coherency_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	BUG_ON(mvebu_mbus_dt_init(coherency_available()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void __init i2c_quirk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 dev, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * Only revisons more recent than A0 support the offload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * mechanism. We can exit only if we are sure that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * get the SoC revision and it is more recent than A0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		struct property *new_compat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		new_compat->name = kstrdup("compatible", GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		new_compat->length = sizeof("marvell,mv78230-a0-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 						GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		of_update_property(np, new_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void __init mvebu_dt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (of_machine_is_compatible("marvell,armadaxp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		i2c_quirk();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void __init armada_370_xp_dt_fixup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	smp_set_ops(smp_ops(armada_xp_smp_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const char * const armada_370_xp_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	"marvell,armada-370-xp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.l2c_aux_val	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.init_machine	= mvebu_dt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.init_irq       = mvebu_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.restart	= mvebu_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.reserve        = mvebu_memblock_reserve,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.dt_compat	= armada_370_xp_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.dt_fixup	= armada_370_xp_dt_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const char * const armada_375_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	"marvell,armada375",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.l2c_aux_val	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.init_irq       = mvebu_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.init_machine	= mvebu_dt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.restart	= mvebu_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.dt_compat	= armada_375_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const char * const armada_38x_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	"marvell,armada380",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	"marvell,armada385",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.l2c_aux_val	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.init_irq       = mvebu_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.restart	= mvebu_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.dt_compat	= armada_38x_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const char * const armada_39x_dt_compat[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	"marvell,armada390",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	"marvell,armada398",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.l2c_aux_val	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.init_irq       = mvebu_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.restart	= mvebu_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.dt_compat	= armada_39x_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MACHINE_END