^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/arm/mach-mv78xx0/pcie.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PCIe functions for Marvell MV78xx0 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <video/vga.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <plat/pcie.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mv78xx0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct pcie_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 maj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 root_bus_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) spinlock_t conf_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) char mem_space_name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct pcie_port pcie_port[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int num_pcie_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct resource pcie_io_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 pcie_port_size[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void __init mv78xx0_pcie_preinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 size_each;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pcie_io_space.name = "PCIe I/O Space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pcie_io_space.end =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pcie_io_space.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (request_resource(&iomem_resource, &pcie_io_space))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) panic("can't allocate PCIe I/O space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (num_pcie_ports > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) panic("invalid number of PCIe ports");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) size_each = pcie_port_size[num_pcie_ports];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) start = MV78XX0_PCIE_MEM_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) for (i = 0; i < num_pcie_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pcie_port *pp = pcie_port + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "PCIe %d.%d MEM", pp->maj, pp->min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pp->res.name = pp->mem_space_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pp->res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pp->res.start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pp->res.end = start + size_each - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) start += size_each;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (request_resource(&iomem_resource, &pp->res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) panic("can't allocate PCIe MEM sub-space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pp->res.start, resource_size(&pp->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) i * SZ_64K, SZ_64K, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pcie_port *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (nr >= num_pcie_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pp = &pcie_port[nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sys->private_data = pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pp->root_bus_nr = sys->busnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Generic PCIe unit setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) orion_pcie_setup(pp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Don't go out when trying to access nonexisting devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * on the local bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (bus == pp->root_bus_nr && dev > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pci_sys_data *sys = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct pcie_port *pp = sys->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_lock_irqsave(&pp->conf_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) spin_unlock_irqrestore(&pp->conf_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pci_sys_data *sys = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct pcie_port *pp = sys->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spin_lock_irqsave(&pp->conf_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spin_unlock_irqrestore(&pp->conf_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct pci_ops pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .read = pcie_rd_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .write = pcie_wr_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void rc_pci_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Prevent enumeration of root complex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (dev->bus->parent == NULL && dev->devfn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev->resource[i].start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev->resource[i].end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev->resource[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int __init mv78xx0_pcie_scan_bus(int nr, struct pci_host_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pci_sys_data *sys = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (nr >= num_pcie_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) list_splice_init(&sys->resources, &bridge->windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bridge->dev.parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bridge->sysdata = sys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) bridge->busnr = sys->busnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bridge->ops = &pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return pci_scan_root_bus_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct pci_sys_data *sys = dev->bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct pcie_port *pp = sys->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct hw_pci mv78xx0_pci __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .nr_controllers = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .preinit = mv78xx0_pcie_preinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .setup = mv78xx0_pcie_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .scan = mv78xx0_pcie_scan_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .map_irq = mv78xx0_pcie_map_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void __init add_pcie_port(int maj, int min, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (orion_pcie_link_up(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pcie_port *pp = &pcie_port[num_pcie_ports++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) printk("link up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pp->maj = maj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pp->min = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pp->root_bus_nr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pp->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_lock_init(&pp->conf_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) memset(&pp->res, 0, sizeof(pp->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) printk("link down, ignoring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __init mv78xx0_pcie_init(int init_port0, int init_port1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (init_port0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) add_pcie_port(0, 0, PCIE00_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) add_pcie_port(0, 1, PCIE01_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) add_pcie_port(0, 2, PCIE02_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) add_pcie_port(0, 3, PCIE03_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (init_port1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) add_pcie_port(1, 0, PCIE10_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) add_pcie_port(1, 1, PCIE11_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) add_pcie_port(1, 2, PCIE12_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) add_pcie_port(1, 3, PCIE13_VIRT_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pci_common_init(&mv78xx0_pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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