^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Generic definitions for Marvell MV78xx0 SoC flavors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MV781x0 and MV782x0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __ASM_ARCH_MV78XX0_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __ASM_ARCH_MV78XX0_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "irqs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Marvell MV78xx0 address maps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * c0000000 PCIe Memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * f0800000 PCIe #0 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * f0900000 PCIe #1 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * f0a00000 PCIe #2 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * f0b00000 PCIe #3 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * f0c00000 PCIe #4 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * f0d00000 PCIe #5 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * f0e00000 PCIe #6 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * f0f00000 PCIe #7 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * f1000000 on-chip peripheral registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * virt phys size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * fe400000 f102x000 16K core-specific peripheral registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * fee00000 f0800000 64K PCIe #0 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * fee10000 f0900000 64K PCIe #1 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * fee20000 f0a00000 64K PCIe #2 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * fee30000 f0b00000 64K PCIe #3 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * fee40000 f0c00000 64K PCIe #4 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * fee50000 f0d00000 64K PCIe #5 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * fee60000 f0e00000 64K PCIe #6 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * fee70000 f0f00000 64K PCIe #7 I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * fec00000 f1000000 1M on-chip peripheral registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MV78XX0_CORE_REGS_SIZE SZ_16K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MV78XX0_PCIE_IO_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MV78XX0_REGS_PHYS_BASE 0xf1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MV78XX0_REGS_SIZE SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MV78XX0_PCIE_MEM_SIZE 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Core-specific peripheral registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BRIDGE_WINS_CPU0_BASE (MV78XX0_CORE0_REGS_PHYS_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BRIDGE_WINS_CPU1_BASE (MV78XX0_CORE1_REGS_PHYS_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BRIDGE_WINS_SZ (0xA000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Register Map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DDR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DDR_WINDOW_CPU0_BASE (DDR_PHYS_BASE + 0x1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DDR_WINDOW_CPU1_BASE (DDR_PHYS_BASE + 0x1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DDR_WINDOW_CPU_SZ (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Supported devices and revisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MV78X00_Z0_DEV_ID 0x6381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MV78X00_REV_Z0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MV78100_DEV_ID 0x7810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MV78100_REV_A0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MV78100_REV_A1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MV78200_DEV_ID 0x7820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MV78200_REV_A0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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